CRMIX

HS

Phase or CLK

Leading Edge

Modulation

CV

RAMP

ERROR

AMP

RAMP

75K

SS

FB

COMP

PWM

40k

100k

0.7V

0.75V

CLK

Isync x 3

CRMIX

CV

BUFFER

LM5115

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SNVS343E – MARCH 2005 – REVISED MARCH 2013

Error Amplifier and Soft-Start (FB, CO, & COMP, SS)

An internal wide bandwidth error amplifier is provided within the LM5115 for voltage feedback to the PWM

controller. The amplifier’s inverting input is connected to the FB pin. The output of the auxiliary converter is

regulated by connecting a voltage setting resistor divider between the output and the FB pin. Loop compensation

networks are connected between the FB pin and the error amplifier output (COMP). The amplifier’s non-inverting

input is internally connected to the SS pin. The SS pin is biased at 0.75V by a resistor divider connected to the

internal 1.27V bandgap reference. When the VCC voltage is below the UVLO threshold, the SS pin is discharged

to ground. When VCC rises and exceeds the positive going UVLO threshold (4.25V), the SS pin is released and

allowed to rise. If an external capacitor is connected to the SS pin, it will be charged by the internal resistor

divider to gradually increase the non-inverting input of the error amplifier to 0.75V. The equivalent impedance of

the SS resistor divider is nominally 60k

Ω which determines the charging time constant of the SS capacitor.

During start-up, the output of the LM5115 converter will follow the exponential equation:

where

•

Rss = internal resistance of SS pin (60k

Ω)

•

Css = external Soft-Start capacitor

•

VOUT(final) = regulator output set point

(3)

The initial

Δv / Δt of the output voltage is VOUT(final) / Rss x Css and VOUT will be within 1% of the final

regulation level after 4.6 time constants or when t = 4.6 x Rss x Css.

Pull-up current for the error amplifier output is provided by an internal 300µA current source. The PWM threshold

signal at the COMP pin can be controlled by either the open drain error amplifier or the open drain current

amplifier connected through the CO pin to COMP. Since the internal error amplifier is configured as an open

drain output it can be disabled by connecting FB to ground. The current sense amplifier and current limiting

function will be described in a later section.

Leading Edge Pulse Width Modulation

Unlike conventional voltage mode controllers, the LM5115 implements leading edge pulse width modulation. A

shown in Figure 15. The ramp signal and the output of the error amplifier (COMP) are combined through a

resistor network to produce a voltage ramp with variable dc offset (CRMIX in Figure 15). The high side MOSFET

which drives the HS pin is held in the off state at the beginning of the phase signal. When the voltage of CRMIX

exceeds the internal threshold voltage CV, the PWM comparator turns on the high side MOSFET. The HS pin

rises and the MOSFET delivers current from the main converter phase signal to the output of the auxiliary

regulator. The PWM cycle ends when the phase signal falls and power is no longer supplied to the drain of the

high side MOSFET.

Figure 15. Synchronization and Leading Edge Modulation

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