LX1669

PRODUCT DA T ABOOK 1996/1997

Copyright © 1999

Rev. 1.0

4/99

8

THEOR Y OF OPERATION

OVER-CURRENT PROTECTION (OCP) and HICCUP

The over-current protection function is tripped when the induc-

tor current exceeds its maximum limit. The current is sensed

with a resistor in series with the inductor. When the voltage

across the sensing resistor exceeds the 60mV threshold, the OCP

comparator outputs a signal to reset the PWM latch and to start

hiccup mode. The soft-start capacitor, C

(10 times slower than when being charged up by R

voltage on the SS/ENABLE pin reaches a 0.3V threshold, hiccup

finishes and the circuit soft-starts again. During hiccup, the top

MOSFET is OFF and the bottom MOSFET remains ON.

Hiccup is disabled during the soft-start interval, allowing the

circuit to start up with the maximum current. If the rise speed

of the output voltage is too fast, the required charging current to

the output capacitor may be higher than the limit-current. In this

case, the peak inductor current is regulated to the limit-current

by the current-sense comparator. The top MOSFET is turned on

at the end of the controlled off-time and is turned off when the

inductor current reaches the limit.

If the inductor current still

reaches its limit after the soft-start finishes, the hiccup is triggered

again. The hiccup ensures the average heat generation on both

MOSFET’s and the average current to be much less than that in

normal operation, if the output has a short circuit.

OVER-VOLTAGE PROTECTION (OVP)

The output voltage is inherently protected from an over-voltage

situation because of the peak-voltage control mechanism.

Whenever the V

40mV, the top MOSFET is turned off and the bottom MOSFET is

turned on. In the case that a fault condition occurs where the

output voltage exceeds the 117% V

SET

threshold, the OVP

comparator will pull up the OVP pin to 2 volts. The OVP pin has

a 40mA source current capability, so it can be used to trigger an

SCR crowbar or shut off the main power supply.

OFF-TIME CONTROL and SWITCHING FREQUENCY

An internal timer controls the off-time of the top MOSFET so that

the switching frequency is constant at 250kHz under steady-state

operation. The timer begins timing once the PWM latch is reset

and set the PWM flip-flop again when the off-time finishes. The

off-time is controlled to be:

T

For a buck converter, the switching frequency is

f

Therefore, the switching frequency is nearly constant in steady

state operation.

During transient loading, the top drive can

remain switched on or off until the output voltage is within

specification (see Figure 5) in order to reduce transient response

time.

POWER GOOD OUTPUT

An open-collector output, PWRGD, is provided to indicate the

status of the output voltages. PWRGD presents high impedance

when the switcher output voltage is within ±10% of its set

voltage. Otherwise, PWRGD presents a low impedance path to

ground.

FIGURE 5 — Top FET Drive During Transient Load Conditions

V

Top FET Drive

Output Voltage

(2.8V Set Point)

13A Load Transient

(in 390ns)