Preliminary Information

MT93L16

21

Address:

3Ah Read

Receive (Rout) Peak Detect Register

1 (ROPD1)

Power Up

Reset 00h

These peak detector registers allow the user to monitor the receive out signal (Rout) peak level at reference point R3 (see

Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte

is in Register 2 and the low byte is in Register 1.

Address:

3Bh Read

Receive (Rout) Peak Detect Register

2 (ROPD2)

Power Up

Reset 00h

See Above description

Address:

36h Read

Send (Sin) Peak Detect Register

1 (SIPD1)

Power Up

Reset 00h

These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see

Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte

is in Register 2 and the low byte is in Register 1.

Address:

37h Read

Send (Sin) Peak Detect Register

2 (SIPD2)

Power Up

Reset 00h

See above description

76

5

0

43

1

2

LSB

MSB

76

5

0

43

1

2

LSB

MSB

76

5

0

43

1

2

LSB

MSB

76

5

0

43

1

2

LSB

MSB