ADC14X250 datasheet(39/69 Pages) TI1

39 / 69 page

ADC14X250

www.ti.com

SLASE49 – DECEMBER 2015

Product Folder Links: ADC14X250

Submit Documentation Feedback

Table 22. JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A] (continued)

Bit

Field

Type

Reset

Description

[5]

SYNC

Read

N/A

JESD204B link synchronization request status

This bit is cleared when a synchronization request is received at the

SYNCb input.

0 : Synchronization request received at the SYNCb input and

synchronization is in progress

1 : Synchronization not requested

Note:

•

SYNCb must be asserted for at least four local frame clocks before

synchronization is initiated. The SYNC status bit reports the status

of synchronization, but does not necessarily report the current

status of the signal at the SYNCb input.

[4]

REALIGN

Read or write

N/A

SYSREF re-alignment status

This bit is set when a SYSREF event causes a shift in the phase of the

internal frame or LMFC clocks.

Note:

•

Write a 1 to REALIGN to clear the bit field to a 0 state.

•

SYSREF events that do not cause a frame or LMFC clock phase

adjustment do not set this register bit.

•

If CLK_RDY becomes low, this bit is cleared.

[3]

ALIGN

Read or write

N/A

SYSREF alignment status

This bit is set when the ADC has processed a SYSREF event and

indicates that the local frame and multi-frame clocks are now based on

a SYSREF event.

Note:

•

Write a 1 to ALIGN to clear the bit field to a 0 state.

•

Rising-edge SYSREF event sets ALIGN bit.

•

If CLK_RDY becomes low, this bit is cleared.

[2]

PLL_LOCK

Read

N/A

PLL lock status. This bit is set when the PLL has achieved lock.

0 : PLL unlocked

1 : PLL locked

[1]

CAL_DONE

Read

N/A

ADC calibration status

This bit is set when the ADC calibration is complete.

0 : Calibration currently in progress or not yet completed

1 : Calibration complete

Note:

•

Calibration must complete before SYSREF detection (SYS_EN)

can be enabled.

•

Calibration must complete before the any clock phase delay

adjustments are made.

[0]

CLK_RDY

Read

N/A

Input clock status

This bit is set when the ADC is powered-up and detects an active clock

signal at the CLKIN input.

0 : CLKIN not detected

1 : CLKIN detected

ADC14X250 Datasheet(PDF) 39 Page - Texas Instruments

ADC14X250 Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL