LAN8820I datasheet(35/83 Pages) MICROCHIP

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DS00001871B-page 35

LAN8820/LAN8820I

4.2

Primary PHY Registers

The primary PHY registers are accessed via the SMI bus. An index is used to access individual primary registers. Pri-

mary PHY register indexes are shown in Table 4-2, "PHY Control and Status Registers". Additional read-only advanced

registers are indirectly accessible via the Advanced Register Address Port and Advanced Register Read Data Port. Sec-

tion 4.3, "Advanced PHY Registers," on page 53 provides detailed information regarding the advanced registers.

Note 1:

All unlisted register index values are not supported and should not be addressed.

The NASR (Not Affected by Software Reset) designation is only applicable when the PHY Soft Reset

(RESET) bit of the Basic Control Register is set.

TABLE 4-2:

PHY CONTROL AND STATUS REGISTERS

Index

(In Decimal)

Basic Control Register

Basic Status Register

PHY Identifier 1 Register

PHY Identifier 2 Register

Auto Negotiation Advertisement Register

Auto Negotiation Link Partner Ability Register

Auto Negotiation Expansion Register

Auto Negotiation Next Page TX Register

Auto Negotiation Next Page RX Register

Master/Slave Control Register

Master/Slave Status Register

Extended Status Register

Link Control Register

10/100 Mode Control/Status Register

10/100 Special Modes Register

Extended Mode Control/Status Register

Advanced Register Address Port

Advanced Register Read Data Port

Control / Status Indications Register

Interrupt Source Flags Register

Interrupt Mask Register

PHY Special Control / Status Register

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