LAN8820I datasheet(44/83 Pages) MICROCHIP

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LAN8820/LAN8820I

DS00001871B-page 44

 2009-2015 Microchip Technology Inc.

4.2.12

EXTENDED STATUS REGISTER

4.2.13

LINK CONTROL REGISTER

Index (In Decimal): 15

Size:

16 bits

Bits

Description

Type

Default

1000BASE-X Full Duplex

0 = PHY not able to perform full duplex 1000BASE-X

1 = PHY able to perform full duplex 1000BASE-X

1000BASE-X Half Duplex

0 = PHY not able to perform half duplex 1000BASE-X

1 = PHY able to perform half duplex 1000BASE-X

1000BASE-T Full Duplex

0 = PHY not able to perform full duplex 1000BASE-T

1 = PHY able to perform full duplex 1000BASE-T

1000BASE-T Half Duplex

0 = PHY not able to perform half duplex 1000BASE-T

1 = PHY able to perform half duplex 1000BASE-T

11:0

RESERVED

Index (In Decimal): 16

Size:

16 bits

Bits

Description

Type

Default

15:10

RESERVED

9:8

Speed Optimize Control

This register sets the number of Auto Negotiation attempts before the Speed

Optimize mechanism reduces the advertised speed.

00 = 7 attempts

01 = 5 attempts

10 = 4 attempts

11 = 3 attempts

Note:

Refer to Section 3.9.5, "Speed Optimizer," on page 29 for additional

information.

R/W

00b

7:6

RESERVED

5:4

Link Break Threshold

Idle error threshold for failing the link, if Link break in enabled.

00 = link break threshold is 10E-8.

01 = link break threshold is 10E-9.

10 = link break threshold is 10E-10.

11 = link break threshold is 10E-11

R/W

10b

Link Break Enable

0 = link break is disabled

1 = link break is enabled

R/W

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