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ADS5294IPFPR Datasheet(PDF) 40 Page - Texas Instruments

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Part # ADS5294IPFPR
Description  Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC
PDF  81 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS5294IPFPR Datasheet(HTML) 40 Page - Texas Instruments

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ADS5294
SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015
www.ti.com
9.6 Register Maps
Table 6. Summary of Functions Supported by Serial Interface (1)(2)(3)(4)
ADDR.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
DESCRIPTION
(HEX)
1: Self-clearing software RESET; . After reset, this bit is set to 0
00
X
RST
0: Normal operation.
X
EN_READOUT
1: READOUT of registers mode;0: Normal operation
01
0 – Disable access to register at address 0xF0
X
EN_HIGH_ADDRS
1 – Enable access to register at address 0xF0
1:Enable SYNC feature to synchronize the test patterns;
0: Normal operation, SYNC feature is disabled for the test patterns.
02
X
EN_SYNC
Note: this bit needs to be set as 1 when software or hardware SYNC
feature is used. see Reg.0x25[8] and 0x25[15]
0A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RAMP_PAT_RESET_VAL
Ramp pattern reset value
1:Channel-specific ADC power-down mode;
X
X
X
X
X
X
X
X
PDN_CH<8:1>
0: Normal operation
1:Partial power-down mode - fast recovery from power-down;
X
PDN_PARTIAL
0: Normal operation
0F
1:Register mode for complete power-down - slower recovery;
X
PDN_COMPLETE
0: Normal operation
1:Configures PD pin for partial power-down mode;
X
PDN_PIN_CFG
0:Configures PD pin for complete power-down mode
1: Channel-specific low-frequency noise suppression mode enable;
14
X
X
X
X
X
X
X
X
LFNS_CH<8:1>
0: LFNS disabled
1: Enables output frame clock to be programmed through a pattern;
X
EN_FRAME_PAT
0: Normal operation on frame clock
1C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ADCLKOUT<13:0>
14-bit pattern for frame clock on ADCLKP and ADCLKN pins
23
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PRBS_SEED<15:0>
PRBS pattern starting seed value lower 16 bits
1: Swaps the polarity of the analog input pins electrically;
X
X
X
X
X
X
X
X
INVERT_CH<8:1>
0: Normal configuration
24
X
X
X
X
X
X
X
PRBS_SEED<22:16>
PRBS seed starting value upper 7 bits
(1)
The unused bits in each register (identified as blank table cells) must be programmed as '0'.
(2)
X = Register bit referenced by the corresponding name and description
(3)
Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.
(4)
Multiple functions in a register can be programmed in a single write operation.
40
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Product Folder Links: ADS5294



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