ADS5294IPFPR datasheet(41/81 Pages) TI1

41 / 81 page

ADS5294

www.ti.com

SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015

Table 6. Summary of Functions Supported by Serial Interface (1)(2)(3)(4) (continued)

ADDR.

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

(HEX)

1: Enables a repeating full-scale ramp pattern on the outputs;

EN_RAMP

0: Normal operation

1:Enables mode wherein output toggles between two defined codes;

DUALCUSTOM_PAT

0: Normal operation

1: Enables mode wherein output is a constant specified code;

SINGLE_CUSTOM_PAT

0: Normal operation

2 MSBs for single custom pattern (and for the first code of the dual

BITS_CUSTOM1<13:12>

custom patterns)

BITS_CUSTOM2<13:12>

2 MSBs for second code of the dual custom patterns

1: Software sync bit for test patterns on all 8 CHs;

TP_SOFT_SYNC

0: No sync. Note: in order to synchronize the digital filters using the

SYNC pin, this bit must be set as 0.

1: PRBS test pattern enable bit;

PRBS_TP_EN

0: PRBS test pattern disabled

PRBS_MODE_2

PRBS 9 bit LFSR (23bit LFSR is default)

1: Enable PRBS seed to be chosen from register 0x23 and 0x24;

PRBS_SEED_FROM_REG

0: Disabled

1: Enable the external SYNC feature for syncing test patterns.

TP_HARD_SYNC

0: Inactive. Note: in order to synchronize the digital filters using the

SYNC pin, this bit must be set as 0.

12 lower bits for single custom pattern (and for the first code of the

BITS_CUSTOM1<11:0>

dual custom pattern).

BITS_CUSTOM2<11:0>

12 lower bits for second code of the dual custom pattern

Enables the bit order output.

EN_BITORDER

0 = byte-wise, 1 = word-wise

Selects between byte-wise and bit-wise

1: bit-wise, odd bits come out on one wire and even bits come out on

BIT_WISE

other wire

0: byte-wise, upper bits on one wire and lower bits on other wire

Note: D15 must be set to '0' for this mode

1: Output format is one sample on one LVDS wire and next sample

on other LVDS wire.

EN_WORDWISE__BY_CH<7:0>

0: Data comes out in 2-wire mode with upper set of bits on one

channel and lower set of bits on the other.

Note: D15 must set to '1' for this mode.

1: Enables filter blocks - global control;

GLOBAL_EN_FILTER

0: Inactive

1: Enables channel averaging mode;

EN_CHANNEL_AVG

0: Inactive

GAIN_CH1<3:0>

Programmable gain - Channel 1

GAIN_CH2<3:0>

Programmable gain - Channel 2

GAIN_CH3<3:0>

Programmable gain - Channel 3

GAIN_CH4<3:0>

Programmable gain - Channel 4

Submit Documentation Feedback

Product Folder Links: ADS5294

ADS5294IPFPR Datasheet(PDF) 41 Page - Texas Instruments

ADS5294IPFPR Datasheet(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL