M24C16-DRDW8TG datasheet(11/39 Pages) STMICROELECTRONICS

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M24C16-DRE

Device operation

3.5

Device addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, as

shown in Table 2 .

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding memory device gives an

acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not

match the device select code, it deselects itself from the bus, and goes into Standby mode.

Note:

A: significant address bit.

X: bit is Don’t Care.

Table 2. Device select code

Device type identifier (1)

Chip Enable address

When accessing the

memory

A10

When accessing the

identification page

101

1. The most significant bit, b7, is sent first.

Table 3. Significant address bits

Memory

(Device type identifier = 1010b)

Identification page

(Device type identifier = 1011b)

Random

Address Read

Write

Read

Identification

page

Write

Identification

page

Lock

Identification

page

Read lock status

b3 (1)

A10

XXX

see Section 4.2.5

b2 (1)

b1 (1)

1. Address bits defined inside the DeviceSelect code (see Table 2).

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