MSP430F6433IPZ datasheet(32/119 Pages) TI1

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MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433

SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015

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5.25 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SVSLE = 0, PMMCOREV = 2

I(SVSL)

SVSL current consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

200

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

2.0

µA

SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1

2.5

tpd(SVSL)

SVSL propagation delay

µs

SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0

SVSLE = 0

→1, SVSLFP = 1

12.5

t(SVSL)

SVSL on/off delay time

µs

SVSLE = 0

→1, SVSLFP = 0

100

5.26 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SVMLE = 0, PMMCOREV = 2

I(SVML)

SVML current consumption

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

200

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

2.0

µA

SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1

2.5

tpd(SVML)

SVML propagation delay

µs

SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0

SVMLE = 0

→1, SVMLFP = 1

12.5

t(SVML)

SVML on or off delay time

µs

SVMLE = 0

→1, SVMLFP = 0

100

5.27 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fMCLK ≥ 4 MHz

6.5

Wake-up time from LPM2,

PMMCOREV = SVSMLRRL = n

tWAKE-UP-FAST

LPM3, or LPM4 to active

(where n = 0, 1, 2, or 3),

µs

1 MHz < fMCLK <

8.0

mode(1)

SVSLFP = 1

4 MHz

Wake-up time from LPM2,

PMMCOREV = SVSMLRRL = n

tWAKE-UP-SLOW

LPM3 or LPM4 to active

(where n = 0, 1, 2, or 3),

150

165

µs

mode(2)

SVSLFP = 0

Wake-up time from LPM3.5 or

tWAKE-UP-LPM5

LPM4.5 to active mode(3)

Wake-up time from RST or

tWAKE-UP-RESET

BOR event to active mode(3)

(1)

This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wake-up times are possible with SVSL and SVML in full

performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while

operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx

and MSP430x6xx Family User's Guide (SLAU208).

(2)

This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSL and SVML are in normal mode (low

current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while operating in LPM2,

LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx

Family User's Guide (SLAU208).

(3)

This value represents the time from the wake-up event to the reset vector execution.

Specifications

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Product Folder Links: MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433

MSP430F6433IPZ Datasheet(PDF) 32 Page - Texas Instruments

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