UT8SF2M32MCPC datasheet(6/27 Pages) AEROFLEX

6 / 27 page

36-00-01-006

Ver.

1.9.4

Aeroflex Microelectronics Solutions - HiRel

DEVICE OPERATION

The UT8SF2M32 is synchronous flow-thru SSRAM designed

specifically to eliminate wait states during Write/Read or Read/

Write transitions. All synchronous inputs are registered on the

rising edge of clock. The clock signal is enabled by the Clock

Enable input (CEN). When CEN is HIGH, the clock signal is

disregarded and all internal states are maintained. All

synchronous operations are qualified by CEN. Once power-up

requirements have been satisfied, the input clock may only be

stopped during sleep (ZZ is HIGH) or shutdown mode

(SHUTDOWN is HIGH). Maximum access delay from the

rising edge of clock (tCQV) is 11.5ns (80MHz device).

Access is initiated by asserting all three Chip Enables

(CS0, CS1, CS2) active at the rising edge of the clock with

Clock Enable (CEN) and ADV_LD asserted LOW. The

address presented to the device will be registered. Access can

be either a Read or Write operation, depending on the status of

the Write Enable (WE).

Write operations are initiated by the Write Enable (WE) input.

All write commands are controlled by built in synchronous

self-timed circuitry.

Three synchronous Chip Enables (CS0, CS1, CS2) and an

asynchronous Output Enable (OE) simplify memory depth

expansion. All operations (Reads, Writes, and Deselects) are

registered. ADV_LD must be driven LOW once the device has

been deselected in order to load a new address and command

for the next operation.

Single Read Accesses

A read access is initiated when the following device inputs are

present at rising clock edge: CEN is enabled LOW, CS0, CS1,

and CS2 are all enabled, the Write Enable input signal WE is

disabled HIGH and ADV_LD is asserted LOW. The addresses

present at the address inputs A[20:0] are registered and

presented to the memory. Data is available to the bus within

12ns provided OE is enabled LOW. After the first clock of the

read access, the output buffers are controlled by OE and the

internal control logic. OE must be enabled LOW to drive

requested data. During the next rising clock, any operation

(Read/Write/Deselect) may be initiated.

Burst Read Accesses

The UT8SF2M32 has an internal burst counter allowing up to

four reads to be performed from a single address input. A new

address can only be loaded when ADV_LD is driven LOW.

New addresses are loaded into the SSRAM, as described by

the Single Read Access section. The burst counter operates in

either linear or interleave and is controlled by the MODE input

at power up. When MODE pin is LOW, the burst sequence is

linear. The burst sequence is interleaved when MODE is

HIGH. A0 and A1 are controlled by the burst counter. Burst

counter will wrap around when needed. The burst counter

increments anytime ADV_LD is HIGH and CEN is LOW. The

operation selected by the state of WE is latched at the

beginning of the sequence and maintained throughout.

Read Access Error Detection and Correction

The UT8SF2M32 device features an embedded single error

correction double error detection (SECDED) Aeroflex

proprietary error correction scheme. Single bit errors are

corrected during read accesses. Data corrections, to the core

memory, occurs during a separate data scrubbing activities.

Double bit errors are detected and indicated by MBE0, MBE1

and MBEC. The MBE0 output is the multibit error indictor for

the 16 even DQs. The MBE1 output is the multibit error

indicator for 16 odd DQs. MBEC is the combined ORed result

of MBE0 and MBE1. Either MBEC or MBE0 and MBE1 can

be monitored to validate data. If all MBEx signals (MBEC,

MBE0, MBE1) remain LOW during a data output cycle, the

data is valid. If any of the MBE signal pins go active HIGH

during a read activity, the data is invalid and contains an

uncorrectable multibit error. Aeroflex recommends that all DQ

pins be connected to either VDDQ or VSSQ through pull up/

down resistors as DQ[51:0] must not be left floating. The

upper 20 I/O pins DQ[51:32] are used for error code data

storage, and need to be individually connected to soft pull ups

or downs (refer to Table 4 external connections). When the

EDAC is enabled via the EDACEN pin, the upper 20 data I/Os

are ignored during write operations and tri-stated during read

operations. When the EDAC is disabled, the upper 20 data I/

Os may be written and read the same as DQ[31:0].

Single Write Accesses

A write access is initiated when the following device inputs are

present at rising clock edge: CEN is enabled LOW, CS0, CS1,

and CS2 are all enabled, the Write Enable input signal WE,

ADV_LD, and FLSH_PIPE are asserted LOW. The addresses

present at the address inputs A[20:0] are registered and

presented to the memory core. Data I/Os are tri-stated after

tCQZ is satisfied regardless of the state of OE.

During a write operation, data is qualified by the FLSH_ PIPE

input. Input data at DQ[51:0] is registered when FLSH_PIPE

is LOW in conjunction with an active WE, but ignored when

FLSH_PIPE is HIGH with an active WE. In either state of

FLSH_PIPE, commands are shifted through the register

pipeline.

UT8SF2M32MCPC Datasheet(PDF) 6 Page - Aeroflex Circuit Technology

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