7

36-00-01-001

Ver. 1.1.0

Aeroflex Microelectronics Solutions - HiRel

Changing Clock Frequencies

In order to optimize the UT8SP2M48 device operation, users

are required to establish the FREQSEL pin state to a logic

HIGH for CLK input frequencies > 80MHz and a logic LOW

for CLK input frequencies of

frequency and FREQSEL pin state are established at power on.

Both may only be changed while in SLEEP mode (reference

Table 6).

External Connections

required to be connected between device pin EXTRES (R15)

In order to ensure proper operation in conjunction with JTAG

boundary scan (reference applications note MEM-AN-005),

Aeroflex requires that specific package pins be biased through

of these required external biases.

Notes:

1. NUIL = Not Used Input Low

2. NUIH = Not Used Input High

through >10kΩ resistors.

Notes:

* All chip selects active when L, at least one chip select inactive when H

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW.

2. Write is defined by WE and BWEx

3. When a Write cycle is detected, all I/Os are tri-stated.

4. The DQ pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally

during Write cycles. During a Read cycle DQs = tri-state when OEis inactive or when

the device is deselected and DQs= data when OE is active.

Table 5. External Bias Conditions

Signal Name

Package Pin

Bias Condition

H1, H20, N1, N2,

N19, N20, P13,

R8, R10, R12,

R16

P16, R7, R13

TDO

R5

TCK

R9

ref Table 7

Operation

Address

Used

CSx*

ZZ

SHUT

DOWN

ADV_LD

WE

BWEx

OE

CEN

CLK

DQs

Standby Mode

None

H

L

L

L

X

X

X

L

L-H

3-State

Continue Deselect

None

X

L

L

H

X

X

X

L

L-H

3-State

Read Cycle (Start Burst)

External

L

L

L

L

H

X

L

L

L-H

Data Out

Read Cycle (Cont. Burst)

Next

X

L

L

H

X

X

L

L

L-H

Data Out

NOP/Dummy Read

(Start)

External

L

L

L

L

H

X

H

L

L-H

3-State

NOP/Dummy Read

(Cont.)

Next

X

L

L

H

X

X

H

L

L-H

3-State

Write Cycle (Start Burst)

External

L

L

L

L

L

L

X

L

L-H

Data In

Write Cycle (Cont. Burst)

Next

X

L

L

H

X

L

X

L

L-H

Data In

Dummy Write (Start)

None

L

L

L

L

L

H

X

L

L-H

3-State

Dummy Write (Cont.

Burst)

Next

X

L

L

H

X

H

X

L

L-H

3-State

Clock Inhibit (Stall)

N/A

X

L

L

X

X

X

X

H

L-H

N/A

Sleep Mode

N/A

H

H

L

X

X

X

X

X

X

3-State

Shutdown Mode

None

X

X

H

X

X

X

X

X

X

3-State