7

Table 3. Typical Cell Delays

Note:

1. All specifications in ns (typical). Output load capacitance is 50pF. Fanout loading for input buffers and gates is the equivalent of two gate input loads.

CELL

OUTPUT

TRANSITION

PROPAGATION

Internal Gates

INV1, Inverter

HL

.15

.16

LH

.23

.29

INV4, Inverter 4X

HL

.06

.07

LH

.10

.16

NAND2, 2-Input NAND

HL

.19

.25

LH

.22

.33

NOR2, 2-Input NOR

HL

.16

.22

LH

.32

.45

DFF - CLK to Q

HL

.81

1.12

LH

.76

1.06

HL

.75

1.05

LH

.61

.85

Output Buffers

OC5050N4, CMOS

HL

3.85

2.15

LH

4.66

3.76

OT5050N4, TTL, 4mA

HL

5.58

5.49

LH

2.52

2.93

OT5050N12, TTL, 12mA

HL

2.42

LH

1.29

Input Buffers

IC5050, CMOS

HL

.81

1.07

LH

1.16

1.18

IT5050, TTL

HL

1.39

1.12

LH

1.16

1.30