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Copyright © Azoteq 2015

IQS211 Datasheet v1.3

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November 2015

Figure 4.2 How to use RDY signal on clock line

Communications may be initiated at any time from clock low-to-high transition plus 40us until

20ms thereafter, when the communications window closes. Polling should be done within this

time window in order to communicate with the device. If now communications are done the

window will time out. If communications are completed with a stop command, the window will

close and sampling will continue after a sleep period.

*Erata: After changing register 0xC7 (memory map) in this mode, it is required to read

any other register in order to activate the chosen user interface (such as a standalone

mode) before sending a stop command.

4.3 I2C polling with RDY on clock and wake-up on pin change (111)

This I2C mode is aimed at applications that require the flexibility of I2C settings, but requires

wake-up functionality from the master side. A ready indication is also given on the clock line to

enable the master to efficiently handle the available communications window.

The wake-up on pin change prevents this configuration from being used along with other

devices on the bus.

Scan time

Sample time

Processing

VDDHI

CLK

0V

Delay before

communication

window 40us

Communication

timeout 20ms

Increased Scan time

No communication initiated

time

(not to scale)

Successful communications

(initiated by master)