PI6C48545 datasheet(2/5 Pages) PERICOM

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PI6C48545

3.3V Low Skew 1-to-4

LVTTL/LVCMOS to LVDS Fanout Buffer

PS8770

06/23/05

Pin Description

Name

Pin #

Type

Description

GND

1, 9, 13

Connect to Ground

CLK_EN

I_PU

Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx

outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 80kΩ

pull up.

CLK_SEL

I_PD

Clock select input. When high, selects CLK1 input. When low, selects CLK0 input.

LVCMOS/LVTTL level with 80kΩ pull down.

CLK0

I_PD

LVCMOS / LVTTL clock input

CLK1

I_PD

LVCMOS / LVTTL clock input

5, 7

No internal connection.

I_PU

Output Enable. Controls outputs Q0, nQ0 through Q3, nQ3.

VCC

10, 18

Connect to 3.3V.

Q3, nQ3

11, 12

Differential output pair, LVDS interface level.

Q2, nQ2

14, 15

Differential output pair, LVDS interface level.

Q1, nQ1

16, 17

Differential output pair, LVDS interface level.

Q0, nQ0

19, 20

Differential output pair, LVDS interface level.

Notes:

1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up.

Pin Characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

CIN

Input Capacitance

R_pullup

Input Pullup Resistance

kΩ

R_pulldown

Input Pulldown Resistance

Control Input Function Table

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Source

Q0:Q3

nQ0:nQ3

CLK0

Diasbled: Low

Diasbled: High

CLK1

Disabled: Low

Disabled: High

CLK0

Enabled

CLK1

Enabled

HiZ

Notes:

1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.

PI6C48545 Datasheet(PDF) 2 Page - Pericom Semiconductor Corporation

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