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PI6C49016

Rev. B

06/25/13

PI6C49016

Low Power Networking Clock Generator

Electrical Characteristics - 100MHz Differential Push-Pull Outputs

Unless otherwise specified, V

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Output Frequency

100

MHz

Cycle-to-Cycle Jitter

T

CC/Jitter

150

ps

Peak-to-Peak Phase Jitter

PCIe Gen1 filter function

86

PCIe 2.0 RMS Phase Jitter

J

RM52.0

PCIe 2.0 Test Method @

100 MHz Output

3.1

ps

Spread Range

-0.5

0

%

Spread Rate

32

kHz

Duty Cycle

T

DC

45

50

55

%

Clock Stabilization from

Power Up

3.5

ms

Rising Edge Rate

Note3, 4

0.6

4.0

V/ns

Falling Edge Rate

Note3, 4

0.6

4.0

V/ns

Rise-Fall Matching

Note3, 11

20

Output Skew

T

OSKEW

V

threshold), Intra-pair skew

50

ps

V

threshold), Inter-pair skew

200

ps

Clock Source DC

Impedance(Zo)

Z

C-DC

17

Ω

High-Level Output

Voltage

V

OH

Note2 (Rs = 33ohm)

0.65

0.71

0.85

V

Low-Level Output Voltage

V

OL

-0.20

0

0.05

V

Absolute Crossing Point

Voltage

V

CROSS

Note2, 5, 6

0.25

0.55

V

Variation of V

rising clock edges

V

CROSS

Delta

Note2, 5, 8

140

mV

Average Clock Period

Accuracy

T

PERIOD

AVG

Note3, 9, 10

-300

2800

ppm

Absolute Period (including

jitter and spread spectrum)

T

PERIOD

ABS

Note3, 7

9.847

10.203

ns

Notes:

1. Measured at the end of an 8-inch trace with a 5pF load.

2. Measurement taken from a single-ended waveform.

3. Measurement taken from a differential waveform.

4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time.

The 300 mV measurement window is centered on the differential zero crossing.

5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M–.

6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.

Refers to all crossing points for this measurement.

13-0102