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www.pericom.com

PI6C49019

Rev. B

06/25/13

PI6C49019

Low Power Networking Clock Generator

Decoupling Capacitors

Decoupling capacitors of 0.01 ìF should be connected between VDD and GND as close to the device as possible. Do not share

ground vias between components. Route power from power source through the capacitor pad and then into PI6C49019 pin.

Output Termination

The PCI-Express differential clock outputs of the PI6C49019 are push-pull and require an external series resistor. These resistor

values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section.

PCB Layout Recommendations

For optimum device performance and lowest output phase noise, the following guidelines should be observed.

1. Each 0.01μF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible.

2. No vias should be used between decoupling capacitor and VDD pin.

3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the fer-

rite bead and bulk decoupling from the device is less critical.

4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers

(any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from

PI6C49019.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the

device.

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