PI7C8148B_06 datasheet(13/94 Pages) PERICOM

13 / 94 page

PI7C8148B

ASYNCHRONOUS 2-PORT

PCI-TO-PCI BRIDGE

Page 13 of 94

APRIL 2006 – Revision 1.05

SIGNAL DEFINITIONS

1.1

SIGNAL TYPES

SIGNAL TYPE

DESCRIPTION

Input only

Output only

Power

Tri-state bi-directional

STS

Sustained tri-state. Active LOW signal must be pulled HIGH for 1 cycle

when deasserting.

Open Drain

1.2

SIGNALS

Signals that end with “#” are active LOW.

1.2.1

PRIMARY BUS INTERFACE SIGNALS

Name

Pin Number

Type

Description

P_AD[31:0]

P10, N10, M10, P11,

N11, M11, P12, N12,

M14, L12, L13, L14,

K12, K13, K14, J12,

E14, E13, E12, D14,

D13, D12, C13, B14,

B12, A12, C11, B11,

A11, C10, A10, C9

Primary Address / Data: Multiplexed address and data bus.

Address is indicated by P_FRAME# assertion. Write data is

stable and valid when P_IRDY# is asserted and read data is

stable and valid when P_TRDY# is asserted. Data is transferred

on rising clock edges when both P_IRDY# and P_TRDY# are

asserted. During bus idle, PI7C8148B drives P_AD to a valid

logic level when P_GNT# is asserted.

P_CBE#[3:0]

P14, J13, F12, A13

Primary Command/Byte Enables: Multiplexed command field

and byte enable field. During address phase, the initiator drives

the transaction type on these pins. After that, the initiator drives

the byte enables during data phases. During bus idle, PI7C8148B

drives P_CBE#[3:0] to a valid logic level when P_GNT# is

asserted.

P_PAR

F13

Primary Parity. Parity is even across P_AD[31:0],

P_CBE#[3:0], and P_PAR (i.e. an even number of 1’s). P_PAR

is an input and is valid and stable one cycle after the address

phase (indicated by assertion of P_FRAME#) for address parity.

For write data phases, P_PAR is an input and is valid one clock

after P_IRDY# is asserted. For read data phase, P_PAR is an

output and is valid one clock after P_TRDY# is asserted. Signal

P_PAR is tri-stated one cycle after the P_AD lines are tri-stated.

During bus idle, PI7C8148B drives P_PAR to a valid logic level

when P_GNT# is asserted.

P_FRAME#

J14

STS

Primary FRAME (Active LOW). Driven by the initiator of a

transaction to indicate the beginning and duration of an access.

The de-assertion of P_FRAME# indicates the final data phase

requested by the initiator. Before being tri-stated, it is driven to

a de-asserted state for one cycle.

P_IRDY#

H12

STS

Primary IRDY (Active LOW). Driven by the initiator of a

transaction to indicate its ability to complete current data phase

on the primary side. Once asserted in a data phase, it is not de-

asserted until the end of the data phase. Before tri-stated, it is

driven to a de-asserted state for one cycle.

06-0053

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