PI7C8148B_06 datasheet(21/94 Pages) PERICOM

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PI7C8148B

ASYNCHRONOUS 2-PORT

PCI-TO-PCI BRIDGE

Page 21 of 94

APRIL 2006 – Revision 1.05

2.5

WRITE TRANSACTIONS

Write transactions are treated as either posted write or delayed write transactions. Table 2-2 shows the

method of forwarding used for each type of write operation.

Table 2-2. Write Transaction Forwarding

Type of Transaction

Type of Forwarding

Memory Write

Posted (except VGA memory)

Memory Write and Invalidate

Posted

Memory Write to VGA memory

Delayed

I/O Write

Delayed

Type 1 Configuration Write

Delayed

2.5.1

MEMORY WRITE TRANSACTIONS

Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate” transactions.

When the bridge determines that a memory write transaction is to be forwarded across the bridge, the

bridge asserts DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough

buffer space is available in the posted memory write queue for the address and at least one DWORD of

data. Under this condition, the bridge accepts write data without obtaining access to the target bus. The

bridge can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is

inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the

target. The bridge continues to accept write data until one of the following events occurs:

The initiator terminates the transaction by de-asserting FRAME# and IRDY#.

An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB

boundary, depending on the transaction type.

The posted write data buffer fills up.

When one of the last two events occurs, the bridge returns a target disconnect to the requesting initiator

on this data phase to terminate the transaction.

Once the posted write data moves to the head of the posted data queue, the bridge asserts its request on

the target bus. This can occur while the bridge is still receiving data on the initiator bus. When the

grant for the target bus is received and the target bus is detected in the idle condition, the bridge asserts

FRAME# and drives the stored write address out on the target bus. On the following cycle, the bridge

drives the first DWORD of write data and continues to transfer write data until all write data

corresponding to that transaction is delivered, or until a target termination is received. As long as write

data exists in the queue, the bridge can drive one DWORD of write data each PCI clock cycle; that is,

no master wait states are inserted. If write data is flowing through the bridge and the initiator stalls, the

bridge will signal the last data phase for the current transaction at the target bus if the queue empties.

The bridge will restart the follow-on transactions if the queue has new data.

The bridge ends the transaction on the target bus when one of the following conditions is met:

All posted write data has been delivered to the target.

The target returns a target disconnect or target retry (the bridge starts another transaction to deliver

the rest of the write data).

The target returns a target abort (the bridge discards remaining write data).

06-0053

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