LM98725CCMTSLASHNOPB datasheet(4/145 Pages) TI1

4 / 145 page

LM98725

SNAS474H – APRIL 2009 – REVISED MARCH 2015

www.ti.com

Pin Functions

I/O

TYP

RES

DESCRIPTION

NO.

NAME

PHIC2

Configurable high speed sensor timing output.

PHIC1

Configurable high speed sensor timing output.

SH1

Configurable low speed sensor timing output.

Chip Serial Interface Address Setting Input

CE Level

Address

Float

DGND

CAL

Initiate calibration sequence. Leave unconnected or tie to DGND if unused.

RESET

Active-low master reset. NC when function not being used.

SH_R

External request for an SH pulse.

SDI

Serial Interface Data Input. Can be tied to SDO for compatibility with LM98714 designs.

SDO

Serial Interface Data Output. Can be tied to SDI for compatibility with LM98714 designs.

SCLK

Serial Interface shift register clock.

SEN

Active-low chip enable for the Serial Interface.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

AGND

Analog ground return.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

VREFB

Bottom of ADC reference. Bypass with a 0.1

μF capacitor to ground.

VREFT

Top of ADC reference. Bypass with a 0.1

μF capacitor to ground.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

AGND

Analog ground return.

VCLP

Input Clamp Voltage. Normally bypassed with a 0.1

μF , and a 4.7μF capacitor to AGND.

An external reference voltage may be applied to this pin.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

IBIAS

Bias setting pin. Connect a 9.0 k

Ω 1% resistor to AGND.

AGND

Analog ground return.

OSR

Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.

AGND

Analog ground return.

OSG

Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.

AGND

Analog ground return.

OSB

Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.

CPOFILT2

Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1

μF capacitor to

CPOFILT1.

DGND

Digital ground return.

CPOFILT1

Charge Pump Filter Capacitor.

Bypass this supply pin with a 0.1

μF capacitor to CPOFILT2.

DVB

Digital Core Voltage bypass. Not an input. Bypass with 0.1

μF capacitor to DGND.

INCLK+

Clock Input.

When XTALEN=0

Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when

pin 33 is held at DGND. Otherwise clock is configured for LVDS operation.

When XTALEN=1

Connection to terminal 2 of crystal.

An 18 pF capacitor should be connected from terminal 1 of the crystal to ground.

INCLK-

Clock Input.

When XTALEN=0

Inverting input for LVDS clocks, connect to DGND for CMOS clock.

When XTALEN=1

Connection to terminal 1 of crystal. A 18 pF capacitor should be connected from terminal 1

of the crystal to ground.

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