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LM98725CCMT/NOPB Datasheet(PDF) 1 Page - Texas Instruments |
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LM98725CCMT/NOPB Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 145 page  LM98725 CCD Timing Generator Analog Front End CCD/CIS Sensor Sensor Drivers Image Processor/ ASIC Data Output SPI Motor Controllers CLK SSCG Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LM98725 SNAS474H – APRIL 2009 – REVISED MARCH 2015 LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation 1 Features 3 Description The LM98725 is a fully integrated, high performance 1 • LVDS/CMOS Outputs 16-Bit, 81 MSPS signal processing solution for digital • LVDS/CMOS/Crystal Clock Source with PLL color copiers, scanners, and other image processing Multiplication applications. The LM98725 achieves high-speed • Integrated Flexible Spread Spectrum Clock signal throughput with an innovative architecture utilizing Correlated Double Sampling (CDS), typically Generation employed with CCD arrays, or Sample and Hold • CDS or S/H Processing for CCD or CIS Sensors (S/H) inputs (for higher speed CCD or CMOS image • Independent Gain/Offset Correction for Each sensors). The signal paths utilize 8 bit Programmable Channel Gain Amplifiers (PGA), a ±9-Bit offset correction • Automatic per-Channel Gain and Offset DAC, and independently controlled Digital Black Level correction loops for each input. The Calibration independently programmed PGA and offset DAC • Programmable Input Clamp Voltage allow unique values of gain and offset for each of the • Flexible CCD/CIS Sensor Timing Generator three analog inputs. The signals are then routed to a 81 MHz high performance analog-to-digital converter 2 Applications (ADC). The fully differential processing channel shows exceptional noise immunity with a very low • Multi-Function Peripherals noise floor of –74 dB. The 16-bit ADC has excellent • High-speed Currency/Check Scanners dynamic performance making the LM98725 • Flatbed or Handheld Color Scanners transparent in the image reproduction chain. • High-speed Document Scanners A very flexible integrated Spread Spectrum Clock • Key Specifications: Generation (SSCG) modulator is included to assist with EM compliance and reduce system costs. – Maximum Input Level – 1.2 or 2.4 Volt Modes Device Information(1) – (Both with + or - Polarity Option) PART NUMBER PACKAGE BODY SIZE (NOM) – ADC Resolution: 16-Bit LM98725 TSSOP (56) 14.0 mm × 6.10 mm – ADC Sampling Rate: 81 MSPS (1) For all available packages, see the orderable addendum at the end of the datasheet. – INL: +17/- 28 LSB (typ) – Channel Sampling Rate: 30/30/27 MSPS System Block Diagram – PGA Gain Steps: 256 Steps – PGA Gain Range: 0.62 to 8.3x – Analog DAC Resolution: ±9 Bits – Analog DAC Range: ±307 mV or ±614 mV – Digital DAC Resolution: ±6 Bits – Digital DAC Range: -2048 LSB to + 2016 LSB – SNR: –74dB (@0 dB PGA Gain) – Power Dissipation: 755 mW (LVDS) – Operating Temp: 0 to 70°C – Supply Voltage: 3.3 V Nominal (3.0-V to 3.6-V Range) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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