HM628128DLP-7SL datasheet(12/20 Pages) HITACHI

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HM628128D Series

Low V

CC Data Retention Characteristics (Ta = –20 to +70°C)

Parameter

Symbol

Min

Typ*

Max

Unit

Test conditions*

CC for data retention

2.0

—

Vin

≥ 0V

(1) 0 V

≤ CS2 ≤ 0.2 V or

(2) CS2

≥ V

CC – 0.2 V

CS1

≥ V

CC – 0.2 V

Data retention current

CCDR*

—

1.0

µAV

CC = 3.0 V, Vin ≥ 0 V

(1) 0 V

≤ CS2 ≤ 0.2 V or

(2) CS2

≥ V

CC – 0.2 V,

CS1

≥ V

CC – 0.2 V

CCDR*

—

1.0

µA

CCDR*

—

0.5

µA

Chip deselect to data retention time

CDR

—

See retention waveform

Operation recovery time

RC*

——

Notes: 1. This characteristic is guaranteed only for L-version, 20

µA max. at Ta = –20 to +40°C.

2. This characteristic is guaranteed only for L-SL-version, 3

µA max. at Ta = –20 to +40°C.

3. This characteristic is guaranteed only for L-UL-version, 1

µA max. at Ta = –20 to +40°C.

4. CS2 controls address buffer,

WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls

data retention mode, Vin levels (address,

WE, OE, CS1, I/O) can be in the high impedance state.

CS1 controls data retention mode, CS2 must be CS2

≥ V

CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V.

The

other input levels (address,

WE, OE, I/O) can be in the high impedance state.

5. Typical values are at V

CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

6. t

RC = read cycle time.

Low V

CC Data Retention Timing Waveform (1) (CS1 Controlled)

4.5 V

2.2 V

0 V

CS1

CDR

CS1

≥ V

CC – 0.2 V

Data retention mode

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