®

AS7C4098

AS7C34098

1/13/05; v.1.9

Alliance Semiconductor

P. 7 of 10

AC test conditions

Notes

2

This parameter is sampled, but not 100% tested.

3

For test conditions, see AC Test Conditions, Figures A, B, C.

5

This parameter is guaranteed, but not tested.

6WE is High for read cycle.

7CE and OE are Low for read cycle.

8

Address valid prior to or coincident with CE transition Low.

9

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 Not applicable.

13 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.

Address

CE

LB, UB

WE

Data undefined

High Z

High Z

Data valid

- Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

10%

90%

10%

90%

GND

+3.0V

2 ns

Figure A: Input pulse

255

Ω

480

Ω

GND

+5V

Figure B: 5V Output load

350

Ω

320

Ω

GND

+3.3V

Figure C: 3.3V Output load

168

Ω

Thevenin equivalent: D

OUT

+1.728V (5V and 3.3V)