CS5530 datasheet(44/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

3.1.2

PSERIAL Pin Interface

The majority of the system power management logic is

implemented in the CS5530, but a minimal amount of

logic is contained within the GXLV processor to provide

information that is not externally visible (e.g., graphics

controller).

The processor implements a simple serial communica-

tions mechanism to transmit the CPU status to the

CS5530. The processor accumulates CPU events in an 8-

bit register (defined in Table 3-1) which it transmits serially

every 1 to 10 µs.

The packet transmitter holds the serial output pin (PSE-

RIAL) low until the transmission interval counter has

elapsed. Once the counter has elapsed, the PSERIAL pin

is held high for two clocks to indicate the start of packet

transmission. The contents of the Serial Packet Register

are then shifted out starting from bit 7 down to bit 0. The

PSERIAL pin is held high for one clock to indicate the end

of packet transmission and then remains low until the next

transmission interval. After the packet transmission is

complete, the processor’s Serial Packet Register’s con-

tents are cleared.

The processor’s input clock is used as the clock reference

for the serial packet transmitter.

Once a bit in the register is set, it remains set until the

completion of the next packet transmission. Successive

events of the same type that occur between packet trans-

missions are ignored. Multiple unique events between

packet transmissions accumulate in this register. The pro-

cessor transmits the contents of the serial packet only

when a bit in the Serial Packet Register is set and the

interval counter has elapsed.

For more information on the Serial Packet Register refer-

enced in Table 3-1, refer to the GXLV processor data

book.

The CS5530 decodes the serial packet after each trans-

mission and performs the power management tasks

relatedtovideo retrace.

3.1.2.1

Video Retrace Interrupt

Bit 7 of the “Serial Packet” can be used to generate an

SMI whenever a video retrace occurs within the proces-

sor. This function is normally not used for power manage-

ment but for SoftVGA routines.

Setting F0 Index 83h[2] = 1 (bit details on page 159)

enables this function. A read only status register located

at F1BAR+Memory Offset 00h[5] (bit details on page 180)

can be read to see if the SMI was caused by a video

retrace event.

Table 3-1. GXLV Processor Serial Packet

Bit

Description

Video IRQ: This bit indicates the occurrence of a video

vertical sync pulse. This bit is set at the same time that

the VINT (Vertical Interrupt) bit gets set in the

DC_TIMING_CFG register. The VINT bit has a corre-

sponding enable bit (VIEN) in the DC_TIM_CFG regis-

ter.

CPU Activity: This bit indicates the occurrence of a

level 1 cache miss that was not a result of an instruc-

tion fetch. This bit has a corresponding enable bit in

the PM_CNTL_TEN register.

5:2

Reserved

Programmable Address Decode: This bit indicates

the occurrence of a programmable memory address

decode. The bit is set based on the values of the

PM_BASE register and the PM_MASK register. The

PM_BASE register can be initialized to any address in

the full CPU address range.

Video Decode: This bit indicates that the CPU has

accessed either the display controller registers or the

graphics memory region. This bit has a corresponding

enable bit in the PM_CNTRL_TEN.

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