CS5530 datasheet(93/241 Pages) NSC

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Functional Description (Continued)

channel with the priority of the others rotating accordingly.

This prevents a channel from dominating the system.

The address and word count registers for each channel

are 16-bit registers. The value on the data bus is written

into the upper byte or lower byte, depending on the state

of the internal addressing byte pointer. This pointer can be

cleared by the Clear Byte Pointer command. After this

command, the first read/write to an address or word count

and the byte pointer will point to the high byte. The next

read/write to an address or word-count register will read

or write to the high byte of the 16-bit register and the byte

pointer will point back to the low byte.

When programming the 16-bit channels (Channels 5, 6,

and 7), the address which is written to the base address

base word count for the 16-bit channels is the number of

16-bit words to be transferred, not the number of bytes as

is the case for the 8-bit channels.

TheDMA controller allows theuserto program theactive

level (low or high) of the DRQ and DACK# signals. Since

the two controllers are cascaded together internally on the

chip, these signals should always be programmed with the

DRQ signal active high and the DACK# signal active low.

DMA Shadow Registers

The CS5530 contains a shadow register located at F0

Index B8h (Table 3-39) for reading the configuration of the

DMA controllers. This read-only register can sequence to

read through all of the DMA registers.

DMA Addressing Capability

DMA transfers occur over the entire 32-bit address range

of the PCI bus. This is accomplished by using the DMA

controller’s 16-bit memory address registers in conjunc-

tion with an 8-bit DMA Low Page register and an 8-bit

DMA High Page register. These registers, associated with

each channel, provide the 32-bit memory address capa-

bility. A write to the Low Page register clears the High

Page register, for backward compatibility with the PC/AT

standard. The starting address for the DMA transfer must

be programmed into the DMA controller registers and the

channel’s respective Low and High Page registers prior to

beginning the DMA transfer.

DMA Page Registers and Extended Addressing

The DMA Page registers provide the upper address bits

during DMA cycles. DMA addresses do not increment or

decrement across page boundaries. Page boundaries for

the 8-bit channels (Channels 0 through 3) are every 64

KB and page boundaries for the 16-bit channels (Chan-

nels 5, 6, and 7) are every 128 KB.

Before any DMA operations are performed, the Page

Registers must be written at the I/O Port addresses

shown in Table 4-26 "DMA Page Registers" on page 211

to select the correct page for each DMA channel. The

other address locations between 080h and 08Fh and

480h and 48Fh are not used by the DMA channels, but

canbereadorwritten byaPCIbus master.These regis-

ters are reset to zero at POR. A write to the Low Page

patibility with the PC/AT standard.

For most DMA transfers, the High Page register is set to

zeros and is driven onto PCI address bits AD[31:24] dur-

ing DMA cycles. This mode is backward compatible with

the PC/AT standard. For DMA extended transfers, the

High Page register is programmed and the values are

driven onto the PCI addresses AD[31:24] during DMA

cycles to allow access to the full 4 GB PCI address space.

DMA Address Generation

The DMA addresses are formed such that there is an

upper address, a middle address, and a lower address

portion.

The upper address portion, which selects a specific page,

is generated by the Page registers. The Page registers for

each channel must be set up by the system before a DMA

operation. The DMA Page register values are driven on

PCI address bits AD[31:16] for 8-bit channels and

AD[31:17] for 16-bit channels.

Table 3-39. DMA Shadow Register

Bit

Description

F0 Index B8h

DMA Shadow Register (RO)

Reset Value = xxh

7:0

DMA Shadow (Read Only): This 8-bit port sequences through the following list of shadowed DMA Controller registers.

At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this

register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written

to that location.

The read sequence for this register is:

1. DMA Channel 0 Mode Register

2. DMA Channel 1 Mode Register

3. DMA Channel 2 Mode Register

4. DMA Channel 3 Mode Register

5. DMA Channel 4 Mode Register

6. DMA Channel 5 Mode Register

7. DMA Channel 6 Mode Register

8. DMA Channel 7 Mode Register

9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.)

10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 msec, all other bits are 0)

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