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Revision 3.2

Index 08h-09h

Number of LP/Valid Line Start Register (R/W)

Reset Value = 0004h

15:9

Reserved: Must be set to 0.

8:0

Number of LP / Valid Line Start: This 9-bit value has a different meaning for 1X or 2X display modes. (Refer to Figure 4-

1.)

Number of LP (1X Mode, Index 02h[5] = 0): Number of LP pulses required by the LCD panel in 1X Refresh Mode. Since

some LCD panels may require more LP pulses than the actual number of displayable lines, this feature allows the

required number of LP pulses to be sent.

Valid Line Start (2X Mode, Index 02h[5] = 1): Line count for valid data start after FP_VSYNC in 2X Refresh Mode.

Instead of synthesizing all the LP pulses in 2X Refresh Mode, LP pulses are in fact equivalent to the input FP_HSYNC

with a programmable starting point offset. This valid line count informs the hardware when to look for valid incoming data.

Index 0Ah-0Bh

LP Adjust Register (R/W)

Reset Value = 0001h

15:9

Reserved: Must be set to 0.

8:0

LP Adjust: This 9-bit value defines the number of LP pulses to be lengthened by one extra cycle in order to spread out

the error in LP timing. (Refer to Figure 4-1.)

For example:

DOTCLK

= 40 MHz

Vertical Frequency = 60 Hz

Required # of LP

= 300

LP_END

= DOTCLK / Vsync / # of LP

= 40M / 60 / 300 = 2222.22

≈ 2222

This 0.22 error will introduce a timing error at the last LP pulse before FLM of 1.67 µs (0.22 x 300 x 1/40M). In order to

spread this error out over all LP intervals, LP_ADJUST is set to:

LP_ADJUST

= 0.22 * 300

=66

Index 0Ch-0Dh

LP Start Register (R/W)

Reset Value = 005Ah

15:12

Reserved: Must be set to 0.

11:0

LP Start: 12-bit value that specifies the number of DOTCLK cycles to the start of the next LP pulse from the falling edge

of the last LP before internal VSYNC. (Refer to Figure 4-1.)

Index 0Eh-0Fh

LP End Register (R/W)

Reset Value = 0075h

15:12

Reserved: Must be set to 0.

11:0

LP End: 12-bit value that specifies the number of DOTCLK cycles in duration for updating one line of the LCD panel. This

value is used only in 1X Refresh Mode (Index 02h[5] = 0). (Refer to Figure 4-1.)

Index 10h-11h

FLM Start Register (R/W

Reset Value = 0020h

15:12

Reserved: Must be set to 0.

11:0

FLM Start: 12-bit value that specifies the number of DOTCLK cycles to the start of an FLM pulse from the internal

VSYNC signal rising edge. (Refer to Figure 4-1.)

Index 12h-13h

FLM End Register (R/W)

Reset Value = 0010h

15:12

Reserved: Must be set to 0.

11:0

FLM End: 12-bit value that specifies the number of DOTCLK cycles to the falling edge of the FLM pulse from the falling

edge of the first LP after the FLM pulse started. (Refer to Figure 4-1.)

Table 4-2. CS9210 Registers (Continued)

Bit

Description