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CS9210 Datasheet(PDF) 27 Page - National Semiconductor (TI) |
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CS9210 Datasheet(HTML) 27 Page - National Semiconductor (TI) |
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27 / 39 page ![]() Revision 3.2 27 www.national.com Register Descriptions (Continued) Figure 4-1. LCD Timing Configuration Diagram LP Internal VSYNC LP_START LP_END #1 #2 #N–1 #N 17 DOTCLK cycles in 1X mode Number of LP Possible error without LP_ADJUST SHFCLK FLM_START FLM_END FLM 22 DOTCLK cycles in 2X mode Lengthened pulse from LP_ADJUST Note: Internal VSYNC is a pulse internal to the CS9210, triggered by a rising edge on the FP_VSYNC input. Index 10h[11:0] Index 12h[11:0] Index 0Ch[11:0] Index 0Eh[11:0] Index 0Ah[8:0] |
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