74LVC3G04DP datasheet(1/13 Pages) PHILIPS

Part #	74LVC3G04DP

Description	Triple inverter

PDF	13 Pages

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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1.

General description

The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device

and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using Ioff. The Ioff circuitry

disables the output, preventing the damaging backﬂow current through the device when it

is powered down.

The 74LVC3G04 provides three inverting buffers.

2.

Features

s Wide supply voltage range from 1.65 V to 5.5 V

s 5 V tolerant outputs for interfacing with 5 V logic

s High noise immunity

s Complies with JEDEC standard:

x JESD8-7 (1.65 V to 1.95 V)

x JESD8-5 (2.3 V to 2.7 V)

x JESD8-B/JESD36 (2.7 V to 3.6 V).

s ESD protection:

x HBM EIA/JESD22-A114-B exceeds 2000 V

x MM EIA/JESD22-A115-A exceeds 200 V.

s

±24 mA output drive (V

CC = 3.0 V)

s CMOS low power consumption

s Latch-up performance exceeds 250 mA

s Direct interface with TTL levels

s SOT505-2 and SOT765-1 package

s Speciﬁed from

−40 °C to +85 °C and −40 °C to +125 °C.

74LVC3G04

Triple inverter

Rev. 01 — 4 May 2004

Product data sheet

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74LVC3G04DP Datasheet(PDF) 1 Page - NXP Semiconductors

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