ADC08B200

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SNAS388F – MARCH 2007 – REVISED APRIL 2013

MODES OF OPERATION

The ADC08B200 has several modes of operation. These modes are detailed in Table 3.

The buffer function is controlled by the BSIZE pins, BSIZE0 and BSIZE1, as indicated in Table 4. The buffer can

be bypassed and data read directly from the ADC by setting both of the BSIZE pins low.

Table 3. Modes of Operation

PD

PDADC

WEN

REN

Power State

Operational State

1

x

x

x

Shutdown

Shutdown, non-operational

Buffer Active, ADC

0

1

0

0

ADC powered down, no data can be captured. Buffer may be read.

Shutdown

0

x

0

1

Active

Data is being read from buffer with RCLK

If buffer is bypassed, data is present at output bus. If buffer is used, the chip is

0

0

0

0

Active

ready to capture data to the buffer.

The ADC's digital output is being captured to the buffer. The REN input is

0

0

1

x

Active

ignored.

Buffer Active, ADC

0

1

1

x

PROHIBITED. WEN input is ignored.

Shutdown

Table 4. Buffer Write/Read

BSIZE1

BSIZE0

WEN

REN

Buffer Function

0

0

x

x

Buffer bypassed

0

1

1

x

Write to 256 byte buffer

1

0

1

x

Write to 512 byte buffer

1

1

1

x

Write to 1k byte buffer

0

1

0

1

Read from 256 byte buffer

1

0

0

1

Read from 512 byte buffer

1

1

0

1

Read from 1k byte buffer

TEST PATTERN OUTPUT

The ADC08B200 has a test mode whereby the data outputs have a test pattern which may be used to "train" a

input. There is an on-chip pull-up resistor at this pin, so the device interprets a floating input at this pin to be a

logic high. This pattern is used to test the integrity of the buffer, so the RCLK (Read Clock) input must be used to

get the output pattern.

The test pattern that is put out is a continuously repeated pattern of output codes 00h - FFh - 00h - FFh - 00h.

Note that this pattern repeats as long as the test mode is invoked and RCLK is running, so that every second

time a logic low appears it will be present for two bit times.

APPLICATION EXAMPLE

Figure 47 shows an example of a typical application. The analog input and reference circuits are as described in

Figure 45 and Figure 46, except the input amplifier is shown without any gain and offset adjustments. The overall

nominal gain of the input amplifier circuit is 1.98 and the nominal

−3 dB input bandwidth is about 195 MHz. Note

that this circuit does not show an anti-aliasing filter.

A 50 MHz clock oscillator is used for the input clock source. The MULT0 input grounded and the MULT1 input

high means (from Table 1) that this 50 MHz input clock is multiplied by the internal PLL by 4 to provide a 200

Msps capture rate.

Since the BSIZE0 and BSIZE1 pins are both high, the internal capture buffer size is set to 1,024 bytes (see

Table 2). Data writing to the internal buffer will automatically stop when the buffer is full because the ASW input

is high. The FF (Full Flag) will go high when the buffer is full and data is ready to be read.

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