2003 May 26

9

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset;

positive-edge trigger

74ALVC74

Note

AC WAVEFORMS

maximum clock pulse

frequency

see Figs 6 and 8

1.65 to 1.95

150

275

−

MHz

2.3 to 2.7

200

325

−

MHz

2.7

250

375

−

MHz

3.0 to 3.6

300

425

−

MHz

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

MAX.

UNIT

OTHER

handbook, full pagewidth

MNA422

th

tsu

th

tPHL

tPHL

tW

tPLH

tPLH

tsu

1/fmax

VM

VM

VM

VM

VI

GND

VI

GND

nCP input

nD input

VOH

VOL

nQ output

VOH

VOL

nQ output

Fig.6

The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the

nCP to nD hold times, the output transition times and the maximum clock pulse frequency.

INPUT

1.65 to 1.95 V

0.5

≤ 2.0 ns

2.3 to 2.7 V

0.5

× V

CC

≤ 2.0 ns

2.7 V

1.5 V

2.7 V

≤ 2.5 ns

3.0 to 3.6 V

1.5 V

2.7 V

≤ 2.5 ns