LM25119PSQESLASHNOPB datasheet(3/39 Pages) TI1

3 / 39 page

ExposedPad

VCC1

VCC2

LO1

LO2

PGND1

PGND2

CSG1

CSG2

CS1

CS2

RAMP1

RAMP2

SS1

SS2

VCCDIS

DEMB

LM25119, LM25119-Q1

www.ti.com

SNVS680H – AUGUST 2010 – REVISED MAY 2016

Product Folder Links: LM25119

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5 Pin Configuration and Functions

RTV Package

32-Pin WQFN

Top View

(1)

G = Ground, I = Input, O = Output, P = Power

Pin Functions

TYPE(1)

DESCRIPTION

NO.

NAME

VCC1

Bias supply pin. Locally decouple to PGND1 using a low ESR or ESL capacitor located as close to

controller as possible.

LO1

Low-side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous

MOSFET through a short, low inductance path.

PGND1

Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the

channel1 current sense resistor.

CSG1

Kelvin ground connection to the external current sense resistor. Connect directly to the low side of

the channel1 current sense resistor.

CS1

Current sense amplifier input. Connect to the high side of the channel1 current sense resistor.

RAMP1

PWM ramp signal. An external resistor and capacitor connected between the SW1 pin, the RAMP1

pin and the AGND pin sets the channel1 PWM ramp slope. Proper selection of component values

produces a RAMP1 signal that emulates the current in the buck inductor.

SS1

An external capacitor and an internal 10-µA current source set the ramp rate of the channel1 error

amp reference. The SS1 pin is held low when VCC1 or VCC2 < 4 V, UVLO < 1.25 V or during

thermal shutdown.

VCCDIS

Optional input that disables the internal VCC regulators when external biasing is supplied. If VCCDIS

> 1.25 V, the internal VCC regulators are disabled. The externally supplied bias must be coupled to

the VCC pins through a diode. VCCDIS has a 500-k

Ω pulldown resistor to ground to enable the VCC

regulators when the pin is left floating. The pulldown resistor can be overridden by pulling VCCDIS

above 1.25 V with a resistor divider connected to the external bias supply.

FB1

Feedback input and inverting input of the channel1 internal error amplifier. A resistor divider from the

channel1 output to this pin sets the output voltage level. The regulation threshold at the FB1 pin is

0.8 V.

COMP1

Output of the channel1 internal error amplifier. The loop compensation network must be connected

between this pin and the FB1 pin.

EN2

If the EN2 pin is low, channel2 is disabled. Channel1 and all other functions remain active. The EN2

has a 50-k

Ω pullup resistor to enable channel2 when the pin is left floating.

AGND

Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.

The internal oscillator is set with a single resistor between RT and AGND. The recommended

maximum oscillator frequency is 1.5 MHz which corresponds to a maximum switching frequency of

750 kHz for either channel. The internal oscillator can be synchronized to an external clock by

coupling a positive pulse into RT through a small coupling capacitor.

LM25119PSQE/NOPB Datasheet(PDF) 3 Page - Texas Instruments

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