LM4931ITLSLASHNOPB datasheet(21/50 Pages) TI1

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10 11 12

14 15

PCM_CLK

PCM_SYNC

PCM_SDO/

PCM_SDI

Short frame sync mode (PCM_LONG = 0)

Long frame sync mode (PCM_LONG = 1)

LM4931

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SNAS251E – APRIL 2004 – REVISED MAY 2013

Table 24. PMC_CONFIG (0Ah) (SET = LOGIC 1, CLEAR = LOGIC 0) (continued)

Address

Description

Set the GPIO port function(3):

5:3

GPIO

000

HP_CONNECTED

001

VC_CLOCK

010

GPIO_DATA

5:3

GPIO_SETUP

011

EXT_LS_ENABLE

100

VOICE_ADC_SD

101

VOICE_DAC_SD

110

DAC_LEFT_SD

111

DAC_RIGHT_SD

RSVD

RESERVED(4)

CLASS_D_DITHER

When set enables dither in the class D amplifier

(3)

VC_CLOCK is only supplied over the GPIO port if the voice codec is enabled.

(4)

Reserved bits should be set to zero when programming the associated register.

Audio Interfaces

I2S

The LM4931 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up

to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below:

Figure 6.

PCM

The PCM interface is both master and slave and is compatible with Texas Instruments' AAI, Motorola’s SSI, and

Texas Instrument’s McBSP audio codec interfaces. The protocol is short frame sync MSB first 2’s complement

16 bit linear. The MSB always follows the sync pulse. In the case of companded data the first 8 bits are used and

the interface can be slowed to 8 clock cycles per sync. In PCM_LONG mode the PCM_SYNC signal is inverted

relative to that shown below.

Figure 7.

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