SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

SCK

Data

BIT 1

LSB IN

LSB OUT

BIT 1

MSB OUT

BIT 7

BIT 8

BIT 9

BIT 14

MSB IN

R/W

Address

2

1

4

5

7

6

3

11

9

10

8

SS

SO

SI

12

LP3950

SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013

www.ti.com

Figure 5. SPI Timing Diagram

Limit

Symbol

Parameter

Units

Min

Max

1

Cycle Time

80

ns

2

Enable Lead Time

40

ns

3

Enable Lag Time

40

ns

4

Clock Low Time

40

ns

5

Clock High Time

40

ns

6

Data Setup Time

0

ns

7

Data Hold Time

20

ns

8

Data Access Time

27

ns

9

Output Disable Time

27

ns

10

Output Data Valid

37

ns

11

Output Data Hold Time

0

ns

12

SS Inactive Time

15

ns

(1)

Data guaranteed by design.

I

determined by the capacitance of the bus (typ. 1.8k). Signal timing specifications are shown in Table 2. Unused

maximum bit rate of 200 kbit/s.

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state

of the data line can only be changed when CLK is LOW.

10

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