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LP3950SL/NOPB Datasheet(PDF) 12 Page - Texas Instruments |
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LP3950SL/NOPB Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 38 page  1 8 2 3 7 6 5 8 10 4 9 1 7 SDA SCL ack from slave start msb Chip Address lsb SCL ack from slave w msb Register Add lsb rs r msb DATA lsb stop ack from slave ack from master repeated start data from slave SDA start Id = 36h w ack addr = K¶00 ack rs r ack $GGUHVV K¶00 data ack stop msb Chip Address lsb Id = 36h LP3950 SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013 www.ti.com When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in Figure 10 . Figure 10. I2C Read Cycle Figure 11. I2C Timing Diagram Table 2. I2C Timing Parameters(1) Symbol Parameter Limit Units Min Max 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time (1.65V ≤ VDDIO < 1.80V) 3.2 µs 2 Clock Low Time (1.80V ≤ VDDIO ≤ VDD1,2V) 1.3 µs 3 Clock High Time (1.65V ≤ VDDIO < 1.80V) 1200 ns 3 Clock High Time (1.80V ≤ VDDIO ≤ VDD1,2V) 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time (data output, delay generated by LP3950) 300 900 ns 5 Data Hold Time (data input) 0 900 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 µs Cb Capacitive Load Parameter for Each Bus Line. 10 200 ns Load of One Picofarad Corresponds to One Nanosecond. (1) Data guaranteed by design 12 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP3950 |
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