ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

I

2

C SLAVE address (chip address)

SDA

SCL

S

P

STO

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP5526

SNVS431D – FEBRUARY 2006 – REVISED MARCH 2013

www.ti.com

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

conditions are equivalent, function-wise.

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

addressed must generate an acknowledge after each byte has been received.

eighth bit which is a data direction bit (R/W). The LP5526 address is 59H (101 1001b). For the eighth bit, a “0”

indicates a WRITE and a “1” indicates a READ. This means that the first byte is B2H for WRITE and B3H for

READ. The second byte selects the register to which the data will be written. The third byte contains data to write

to the selected register.

Register changes take an effect at the SCL rising edge during the last ACK from slave.

26

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