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TLK2201RCP Datasheet(PDF) 4 Page - Texas Instruments

Part # TLK2201RCP
Description  ETHERNET TRANSCEIVERS
PDF  24 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLK2201RCP Datasheet(HTML) 4 Page - Texas Instruments

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TLK2201
TLK2201I
ETHERNET TRANSCEIVERS
SLLS420F – JUNE 2000 – REVISED SEPTEMBER 2007
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
RBC0 RBC1
31 30
O
Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output
data on RD0-RD9. The operation of these clocks is dependent upon the receive clock mode
selected. In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0
and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data. In
the normal rate mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned
to the rising edge. In the DDR mode, only RBC0 is valid and operates at 1/10 the serial data rate.
Data is aligned to both the rising and falling edges.
RBCMODE
32
I
Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on
P/D(1)
RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on
RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate
clock is output on RBC0 and RBC1 is held low.
SYNCEN
24
I
Synchronous function enable. When SYNCEN is high, the internal synchronization function is
P/U(2)
activated. When this function is activated, the transceiver detects the K28.5 comma character
(0011111 negative beginning disparity) in the serial data stream and realigns data on byte
boundaries if required. When SYNCEN is low, serial input data is unframed in RD0 - RD9.
SYNC/PASS
47
O
Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the
serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS
test mode (PRBSEN=high), SYNC/PASS outputs the status of the PRBS test results (high=pass).
LOS
26
O
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN. If
magnitude of RXP-RXN > 150 mV, LOS = 1, valid input signalIf magnitude of RXP-RXN < 150 mV
and > 50 mV, LOS is undefinedIf magnitude of RXP-RXN < 50 mV, LOS = 0, loss of signal
MODESEL
15
I
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface.
P/D(3)
When low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected.
The default mode is the TBI.
TEST
LOOPEN
19
I
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
P/D(3)
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
TCK
49
I
Test clock. IEEE1149.1 (JTAG)
JTDI
48
I
Test data input. IEEE1149.1 (JTAG)
P/U(4)
JTDO
27
O
Test data output. IEEE1149.1 (JTAG)
JTRSTN
56
I
Reset signal. IEEE1149.1 (JTAG)
P/U(4)
JTMS
55
I
Test mode select. IEEE1149.1 (JTAG)
P/U(4)
ENABLE
28
I
When this terminal is low, the device is disabled for Iddq testing. RD0 - RD9, RBCn, TXP, and TXN
P/U(4)
are high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is
high, the device operates normally.
PRBSEN
16
I
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
P/D(3)
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs
and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
TESTEN
17
I
Manufacturing test terminal
P/D(3)
POWER
VDD
5, 10, 20,
Supply
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
23, 29, 37,
42, 50, 63
VDDA
53, 57, 59,
Supply
Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter
60
(1)
P/D = Internal pulldown
(2)
P/U = Internal pullup
(3)
P/D = Internal pulldown
(4)
P/U = Internal pullup
4
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Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): TLK2201 TLK2201I



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