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TLK2201RCP Datasheet(PDF) 6 Page - Texas Instruments

Part # TLK2201RCP
Description  ETHERNET TRANSCEIVERS
PDF  24 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLK2201RCP Datasheet(HTML) 6 Page - Texas Instruments

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Receiver Clock Select Mode
td(S)
td(S)
td(H)
td(H)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
RBC0
RBC1
SYNC
RD(0-9)
td(H)
td(S)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
RBC0
SYNC
RD(0-9)
TLK2201
TLK2201I
ETHERNET TRANSCEIVERS
SLLS420F – JUNE 2000 – REVISED SEPTEMBER 2007
There are two modes of operation for the parallel busses. 1)The 10-bit (TBI) mode and 2) 5-bit (DDR) mode.
When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal. 1)
Full-rate clock on RBC0 and 2) Half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate
clock is available on RBC0; refer to Table 1.
Mode Selection
MODESEL
RBCMODE
MODE
FREQUENCY (TLK2201)
FREQUENCY (TLK2201I)
0
0
TBI half-rate
100-125 MHz
120-125 MHz
0
1
TBI full-rate
100-160 MHz
120-160 MHz
1
0
DDR
100-125 MHz
120-125 MHz
1
1
DDR
100-125 MHz
120-125 MHz
In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at
one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is
output with respect to the two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the parallel
bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received data
valid on the rising edge of RBC1. See the timing diagram shown in Figure 2.
Figure 2. Synchronous Timing Characteristics Waveforms (TBI half-rate mode)
In the normal-rate mode, only RBC0 is used and operates at full data rate (i.e., 1.25 Gbps data rate produces a
125 MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode.
See the timing diagram shown in Figure 3.
Figure 3. Synchronous Timing Characteristics Waveforms (TBI full-rate mode)
In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1
is low impedance. The data is clocked bit-0 first, and aligned to the rising edge of RBC0. See the timing diagram
shown in Figure 4.
6
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Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): TLK2201 TLK2201I



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