TMS320C6472ECTZ datasheet(203/269 Pages) TI1

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TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

Table 7-81. DMATCU Receive Channels 0-5 Registers (continued)

HEX ADDRESS RANGE

ACRONYM

0254 1844

DRCH_AFALLOC1

Receive Channel 1 Frame Allocation Register A

0254 1848

DRCH_AFSIZE1

Receive Channel 1 Frame Size Register A

0254 184C

DRCH_AFCNT1

Receive Channel 1 Frame Count Register A

0254 1850 - 0254 185C

Reserved

0254 1860

DRCH_BBASE1

Receive Channel 1 Memory Base Address Register B

0254 1864

DRCH_BFALLOC1

Receive Channel 1 Frame Allocation Register B

0254 1868

DRCH _BFSIZE1

Receive Channel 1 Frame Size Register B

0254 186C

DRCH _BFCNT1

Receive Channel 1 Frame Count Register B

0254 1870 - 0254 187C

Reserved

0254 1880

DRCH_ABASE2

Receive Channel 2 Memory Base Address Register A

0254 1884

DRCH_AFALLOC2

Receive Channel 2 Frame Allocation Register A

0254 1888

DRCH_AFSIZE2

Receive Channel 2 Frame Size Register A

0254 188C

DRCH_AFCNT2

Receive Channel 2 Frame Count Register A

0254 1890 - 0254 189C

Reserved

0254 18A0

DRCH_BBASE2

Receive Channel 2 Memory Base Address Register B

0254 18A4

DRCH_BFALLOC2

Receive Channel 2 Frame Allocation Register B

0254 18A8

DRCH _BFSIZE2

Receive Channel 2 Frame Size Register B

0254 18AC

DRCH _BFCNT2

Receive Channel 2 Frame Count Register B

0254 18B0 - 0254 18BC

Reserved

0254 18C0

DRCH_ABASE3

Receive Channel 3 Memory Base Address Register A

0254 18C4

DRCH_AFALLOC3

Receive Channel 3 Frame Allocation Register A

0254 18C8

DRCH_AFSIZE3

Receive Channel 3 Frame Size Register A

0254 18CC

DRCH_AFCNT3

Receive Channel 3 Frame Count Register A

0254 18D0 - 0254 18DC

Reserved

0254 18E0

DRCH_BBASE3

Receive Channel 3 Memory Base Address Register B

0254 18E4

DRCH_BFALLOC3

Receive Channel 3 Frame Allocation Register B

0254 18E8

DRCH _BFSIZE3

Receive Channel 3 Frame Size Register B

0254 18EC

DRCH _BFCNT3

Receive Channel 3 Frame Count Register B

0254 18F0 - 0254 18FC

Reserved

0254 1900

DRCH_ABASE4

Receive Channel 4 Memory Base Address Register A

0254 1904

DRCH_AFALLOC4

Receive Channel 4 Frame Allocation Register A

0254 1908

DRCH_AFSIZE4

Receive Channel 4 Frame Size Register A

0254 190C

DRCH_AFCNT4

Receive Channel 4 Frame Count Register A

0254 1910 - 0254 191C

Reserved

0254 1920

DRCH_BBASE4

Receive Channel 4 Memory Base Address Register B

0254 1924

DRCH_BFALLOC4

Receive Channel 4 Frame Allocation Register B

0254 1928

DRCH _BFSIZE4

Receive Channel 4 Frame Size Register B

0254 192C

DRCH _BFCNT4

Receive Channel 4 Frame Count Register B

0254 1930 - 0254 193C

Reserved

0254 1940

DRCH_ABASE5

Receive Channel 5 Memory Base Address Register A

0254 1944

DRCH_AFALLOC5

Receive Channel 5 Frame Allocation Register A

0254 1948

DRCH_AFSIZE5

Receive Channel 5 Frame Size Register A

0254 194C

DRCH_AFCNT5

Receive Channel 5 Frame Count Register A

0254 1950 - 0254 195C

Reserved

0254 1960

DRCH_BBASE5

Receive Channel 5 Memory Base Address Register B

0254 1964

DRCH_BFALLOC5

Receive Channel 5 Frame Allocation Register B

0254 1968

DRCH _BFSIZE5

Receive Channel 5 Frame Size Register B

C64x+ Peripheral Information and Electrical Specifications

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