TMS28F004AST datasheet(6/80 Pages) TI1

6 / 80 page

TMS28F004Axy, TMS28F400Axy

524288 BY 8-BIT/

262144 BY 16-BIT

AUTOSELECT BOOT BLOCK FLASH MEMORIES

SMJS829A − JANUARY 1996 − REVISED AUGUST 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

functional block diagram

Counter

Address

Latch

Control

Reduction

Power-

X Decoder

Y Decoder

Y Gating / Sensing

Block

Main

128K-Byte

Block

Main

96K-Byte

Block

Parameter

8K-Byte

Block

Parameter

8K-Byte

Block

Boot

16K-Byte

I/O Logic

Program/

Voltage

Switch

Erase

Machine

State

Write

Machine

State

Command

Data

Comparator

Data

Input

Buffer

Input

Buffer

Status

Identification

Multiplexer

Output

Input Buffer

DQ15/A −1

Output

Buffer

Output

DQ8 − DQ15/A −1

DQ0 − DQ7

A0 −

A17

BYTE

VPP

Input

Buffer

Block

Main

128K-Byte

Block

Main

128K-Byte

architecture

The TMS28F400Axy uses a blocked architecture to allow independent erasure of selected memory blocks. The

block to be erased is selected by using any valid address within that block.

block memory maps

The TMS28F400Axy is available with the block architecture mapped in either of two configurations: the boot

block located at the top or at the bottom of the memory array, as required by different microprocessors. The

TMS28F400AxB (bottom boot block) is mapped with the 16K-byte boot block located at the low-order address

range (00000h to 01FFFh). The TMS28F400AxT (top boot block) is inverted with respect to the TMS28F400AxB

with the boot block located at the high-order address range (3E000h to 3FFFFh). Both of these address ranges

are for word-wide mode. Figure 1 and Figure 2 show the memory maps for these configurations. The

TMS28F004Axy is mapped as the 8-bit configuration of the TMS28F400Axy, except that the least significant

bit (LSB) is A0 instead of A−1.

TMS28F004AST Datasheet(PDF) 6 Page - Texas Instruments

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