TMS570LS1114 datasheet(114/169 Pages) TI1

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TMS570LS1114

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

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Table 7-3. TZ4n Connections for ePWMx Modules

ePWMx

Control for TZ4n =

Control for TZ4n = not(EQEP1ERR)

Control for TZ4n = not(EQEP2ERR)

not(EQEP1ERR OR

EQEP2ERR)

ePWM1

PINMMR41[0] = 1

PINMMR41[0] = 0 AND PINMMR41[1]

PINMMR41[0] = 1 AND PINMMR41[1] = 0 AND

= 1

PINMMR41[2] = 1

ePWM2

PINMMR41[8]

PINMMR41[8] = 0 AND PINMMR41[9]

PINMMR41[8] = 1 AND PINMMR41[9] = 0 AND

= 1

PINMMR41[10] = 1

ePWM3

PINMMR41[16]

PINMMR41[16] = 0 AND

PINMMR41[16] = 1 AND PINMMR41[17] = 0

PINMMR41[17] = 1

AND PINMMR41[18] = 1

ePWM4

PINMMR41[24]

PINMMR41[24] = 0 AND

PINMMR41[24] = 1 AND PINMMR41[25] = 0

PINMMR41[25] = 1

AND PINMMR41[26] = 1

ePWM5

PINMMR42[0]

PINMMR42[0] = 0 AND PINMMR42[1]

PINMMR42[0] = 1 AND PINMMR42[1] = 0 AND

= 1

PINMMR42[2] = 1

ePWM6

PINMMR42[8]

PINMMR42[8] = 0 AND PINMMR42[9]

PINMMR42[8] = 1 AND PINMMR42[9] = 0 AND

= 1

PINMMR42[10] = 1

ePWM7

PINMMR42[16]

PINMMR42[16] = 0 AND

PINMMR42[16] = 1 AND PINMMR42[17] = 0

PINMMR42[17] = 1

AND PINMMR42[18] = 1

7.1.6.3

Trip Zone TZ5n

This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted

whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip

zone input for each ePWMx module in order to prevent the external system from going out of control when

the device clocks are not within expected range (system running at limp clock).

The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the

system module. These are level signals are set until cleared by the application.

7.1.6.4

Trip Zone TZ6n

This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled,

the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the

external system from going out of control when the CPU is stopped.

7.1.7

Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs

A special scheme is implemented in order to select the actual signal used for triggering the start of

conversion on the two ADCs on this device. This scheme is defined in Section 7.4.2.3.

7.1.8

Enhanced Translator-Pulse Width Modulator (ePWMx) Timings

Table 7-4. ePWMx Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tw(SYNCIN)

Synchronization input pulse width

Asynchronous

2 tc(VCLK4)

cycles

Synchronous

2 tc(VCLK4)

cycles

Synchronous, with input

2 tc(VCLK4) + filter width

cycles

filter

Table 7-5. ePWMx Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tw(PWM)

Pulse duration, ePWMx output high or low

33.33

tw(SYNCOUT Synchronization Output Pulse Width

8 tc(VCLK4)

cycles

)

td(PWM)tza

Delay time, trip input active to PWM forced high,

no pin load

OR Delay time, trip input active to PWM forced

low

114

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