TMS570LS1114 datasheet(119/169 Pages) TI1

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TMS570LS1114

www.ti.com

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

Table 7-12. Device-Level Input Connection to eCAPx Modules

Input Signal

Control for Double-Synchronized Connection to

Control for Double-Synchronized and Filtered

eQEPx

Connection to eQEPx

eQEP1A

PINMMR44[16] = 1

PINMMR44[16] = 0 and PINMMR44[17] = 1

eQEP1B

PINMMR44[24] = 1

PINMMR44[24] = 0 and PINMMR44[25] = 1

eQEP1I

PINMMR45[0] = 1

PINMMR45[0] = 0 and PINMMR45[1] = 1

eQEP1S

PINMMR45[8] = 1

PINMMR45[8] = 0 and PINMMR45[9] = 1

eQEP2A

PINMMR45[16] = 1

PINMMR45[16] = 0 and PINMMR45[17] = 1

eQEP2B

PINMMR45[24] = 1

PINMMR45[24] = 0 and PINMMR45[25] = 1

eQEP2I

PINMMR46[0] = 1

PINMMR46[0] = 0 and PINMMR46[1] = 1

eQEP2S

PINMMR46[8] = 1

PINMMR46[8] = 0 and PINMMR46[9] = 1

7.3.4

Enhanced Quadrature Encoder Pulse (eQEPx) Timing

Table 7-13. eQEPx Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tw(QEPP)

QEP input period

Synchronous

2 tc(VCLK4)

cycles

Synchronous, with input

2 tc(VCLK4) + filter width

cycles

filter

tw(INDEXH)

QEP Index Input High Time

Synchronous

2 tc(VCLK4)

cycles

Synchronous, with input

2 tc(VCLK4) + filter width

cycles

filter

tw(INDEXL)

QEP Index Input Low Time

Synchronous

2 tc(VCLK4)

cycles

Synchronous, with input

2 tc(VCLK4) + filter width

cycles

filter

tw(STROBH)

QEP Strobe Input High Time

Synchronous

2 tc(VCLK4)

cycles

Synchronous, with input

2 tc(VCLK4) + filter width

cycles

filter

tw(STROBL)

QEP Strobe Input Low Time

Synchronous

2 tc(VCLK4)

cycles

Synchronous, with input

2 tc(VCLK4) + filter width

cycles

filter

Table 7-14. eQEPx Switching Characteristics

PARAMETER

MIN

MAX

UNIT

td(CNTR)xin

Delay time, external clock to counter increment

4 tc(VCLK4)

cycles

td(PCS-OUT)QEP

Delay time, QEP input edge to position compare sync output

6 tc(VCLK4)

cycles

7.4

Multibuffered 12bit Analog-to-Digital Converter

The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that

enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could

be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given

with respect to ADREFLO unless otherwise noted.

Table 7-15. MibADC Overview

Description

Value

Resolution

12 bits

Monotonic

Assured

Output conversion code

00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI]

Peripheral Information and Electrical Specifications

119

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