MCP1726-0802ESLASHMF datasheet(20/32 Pages) MICROCHIP

20 / 32 page

MCP1726

DS20001936D-page 20

 2005-2014 Microchip Technology Inc.

Junction Temperature Estimate

To estimate the internal junction temperature, the

calculated temperature rise is added to the ambient or

offset temperature. For this example, the worst-case

junction temperature is estimated below.

As can be seen from the result, this application will be

operating above the maximum operating junction

temperature of 125°C. The PCB layout for this

application is very important, as it has a significant

impact on the junction-to-ambient thermal resistance

JA) of the 3x3 DFN package, which is very important

in this application.

Maximum Package Power Dissipation at

70°C Ambient Temperature

From this table you can see the difference in maximum

allowable power dissipation between the 3x3 DFN

package and the 8-pin SOIC package. This difference

is due to the exposed metal tab on the bottom of the

DFN package. The exposed tab of the DFN package

provides a very good thermal path from the die of the

LDO to the PCB. The PCB then acts like a heat sink,

providing more area to distribute the heat generated by

the LDO. When the PCB heat sink area is used, the

JA should be replaced by RJC plus RHS, where

HS is the PCB copper area heat sink thermal

resistance. This will allow for higher maximum power

dissipation compared to the free-air power dissipation

calculated using R

JA.

TJ =TJRISE +TA(MAX)

TJ = 76.3°C + 70.0°C

TJ = 146.3°C

3x3 DFN (64°C/W R



JA)

PD(MAX) = (125°C – 70°C)/64°C/W

PD(MAX) =0.86W

8LD SOIC (163°C/W R



JA)

PD(MAX) = (125°C – 70°C)/163°C/W

PD(MAX) = 0.337W

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