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TNETE2201BPJW Datasheet(PDF) 16 Page - Texas Instruments |
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TNETE2201BPJW Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 28 page ![]() TNETE2201B 1.25GIGABIT ETHERNET TRANSCEIVER SLLS367D − JUNE 1999 − REVISED AUGUST 2007 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL INFORMATION The TNETE2201B incorporates the latest development in TI’s package line. The new patent-pending design, designated the PWP, delivers thermal performance comparing to a heat-spreader design in a true low-profile package. The PWP for the TNETE2201B is designed to maximize heat transfer away from the die through the top of the chip. As seen in Figures 9 and 10 the bottom of the leadframe is deep downset towards the top of the chip, providing a thermal path away from the die and board. All this has been accomplished without exceeding the 1.15 mm height of the TQFP. This package in the 10mm × 10mm TQFP (PJD) provides a thermal resistance RθJA of 40°C/W and the package in the 14mm × 14mm TQFP (PHD) provides a RθJA of 40°C/W. Figure 9. Heat-Spreader Design Figure 10. Leadframe Downset |
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