CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 24 of 51
microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the
transaction from the external master is completed.
When MSTR Mode is cleared from 1 to 0 by a firmware write, an I2C Stop bit is generated.
Bit 6 : Continue/Busy
This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. In other words,
the bit has responded to an interrupt request and has completed the required update or read of the data register. During a
read this bit indicates if the hardware is busy and is locking out additional writes to the I2C Status and Control register. This
locking allows the hardware to complete certain operations that may require an extended period of time. Following an I2C
interrupt, the I2C-compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the
firmware to make one control register write without the need to check the Busy bit.
Bit 5 : Xmit Mode
This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clearing this bit
sets the part in receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I2C
address packet. The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases
always cause transmit mode for the first byte.
Bit 4 : ACK
This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal
on the I2C-compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I2C-compatible bus at the ACK bit
time. During transmits (Xmit Mode = 1), this bit should be cleared.
Bit 3 : Addr
This bit is set by the I2C-compatible block during the first byte of a slave receive transaction, after an I2C start or restart.
The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master
has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.
Bit 2 : ARB Lost/Restart
This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the
Continue and MSTR Mode bits) to perform an I2C restart sequence. The I2C target address for the restart must be written
to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware
during the restart sequence.
Bit 1 : Receive Stop
This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the
firmware terminates the I2C transaction by not acknowledging the previous byte transmitted on the I2C-compatible bus,
e.g., in receive mode if firmware sets the Continue bit and clears the ACK bit.
Bit 0 : I2C Enable
Set this bit to override GPIO definition with I2C-compatible function on the two I2C-compatible pins. When this bit is cleared,
these pins are free to function as GPIOs. In I2C-compatible mode, the two pins operate in open drain mode, independent
of the GPIO configuration setting.
13.0
Processor Status and Control Register
Bit 0: Run
This bit is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is cleared, the processor stops at the end of the current instruction. The processor
remains halted until an appropriate reset occurs (power-on or Watchdog). This bit should normally be written as a ‘1.’
Bit 1: Reserved
Bit 1 is reserved and must be written as a zero.
Bit 2: Interrupt Enable Sense
Processor Status and Control
Address 0xFF
Bit #
7
65
43
21
0
Bit Name
IRQ
Pending
Watchdog
Reset
USB Bus
Reset
Interrupt
Power-on
Reset
Suspend
Interrupt
Enable
Sense
Reserved
Run
Read/Write
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Reset
0
00
10
00
1
Figure 13-1. Processor Status and Control Register
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