M38B53M4-059FP datasheet(45/69 Pages) MITSUBISHI

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MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

Timing setting

Each timing is set by the FLDC mode register, Tdisp time set regis-

ter, Toff1 time set register, and Toff2 time set register.

•Tdisp time setting

Set the Tdisp time by the Tdisp counter count source selection bit of

the FLDC mode register and the Tdisp time set register.

Supposing that the value of the Tdisp time set register is n, the

Tdisp time is represented as Tdisp = (n+1) ! t (t: count source

synchronization).

When the Tdisp counter count source selection bit of the FLDC mode

(C816), the Tdisp time is: Tdisp = (200+1) ! 4 (at XIN= 4 MHz) = 804

µs. When reading the Tdisp time set register, the value in the

counter is read out.

•Toff1 time setting

Set the Toff1 time by the Toff1 time set register.

Supposing that the value of the Toff1 time set register is n1, the

Toff1 time is represented as Toff1 = n1 ! t.

When the Tdisp counter count source selection bit of the FLDC mode

(1E16), Toff1 = 30 ! 4 (at XIN = 4 MHz) = 120 µs.

•Toff2 time setting

Set the Toff2 time by the Toff2 time set register.

Supposing that the value of the Toff2 time set register is n2, the

Toff2 time is represented as Toff2 = n2 ! t.

When the Tdisp counter count source selection bit of the FLDC mode

(B416), Toff2 = 180 ! 4 (at XIN = 4 MHz) = 720 µs.

This Toff2 time setting is valid only for FLD ports which are in the

gradation display mode and whose gradation display control RAM

value is “1.”

FLD automatic display start

To perform FLD automatic display, set the following registers.

•Port P0FLD/port switch register

•Port P2FLD/port switch register

•Port P8FLD/port switch register

•FLDC mode register

•Tdisp time set register

•Toff1 time set register

•Toff2 time set register

•FLD data pointer

FLD automatic display mode is selected by writing “1” to the bit 0 of

the FLDC mode register (address 0EF416), and the automatic dis-

play is started by writing “1” to bit 1. During FLD automatic display,

bit 1 of the FLDC mode register (address 0EF416) always keeps “1,”

and FLD automatic display can be interrupted by writing “0” to bit 1.

Key-scan

When a key-scan is performed with the segment during key-scan

blanking period Tscan, take the following sequence:

1. Write “0” to bit 0 of the FLDC mode register (address 0EF416).

2. Set the port corresponding to the segment for key-scan to the

output port.

3. Perform the key-scan.

4. After the key-scan is performed, write “1” to bit 0 of FLDC mode

s Note

When performing a key-scan according to the above steps 1 to 4,

take the following points into consideration.

1. Do not set “0” in bit 1 of the FLDC mode register (address 0EF416).

2. Do not set “1” in the ports corresponding to digits.

P84 to P87 FLD Output Reverse Function

P84 to P87 are provided with a function to reverse the polarity of the

FLD output. This function is useful in adjusting the polarity when

using an externally installed driver.

The output polarity can be reversed by setting bit 0 of the port P8

FLD output control register to “1.”

M38B53M4-059FP Datasheet(PDF) 45 Page - Mitsubishi Electric Semiconductor

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