DS1922L datasheet(39/48 Pages) DALLAS

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DS1922L/DS1922T

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1-Wire SIGNALING

The DS1922L/T requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on

one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the

presence pulse, the bus master initiates all these signals. The DS1922L/T can communicate at two different

speeds, standard speed and Overdrive speed. If not explicitly set into the Overdrive mode, the DS1922L/T will

communicate at standard speed. While in Overdrive mode the fast timing applies to all waveforms.

To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get

from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to

make this rise is seen in Figure 12 as '

e' and its duration depends on the pullup resistor (RPUP) used and the

capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS1922L/T when determining a

logical level, not triggering any events.

The initialization sequence required to begin any communication with the DS1922L/T is shown in Figure 12. A reset

pulse followed by a presence pulse indicates the DS1922L/T is ready to receive data, given the correct ROM and

memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line

for tRSTL + tF to compensate for the edge. A tRSTL duration of 690µs or longer will exit the Overdrive mode returning

the device to standard speed. If the DS1922L/T is in Overdrive mode and tRSTL is no longer than 80µs the device

will remain in Overdrive mode.

Figure 12. Initialization Procedure “Reset and Presence Pulses”

RESISTOR

MASTER

DS1922L/T

tRSTL

tPDL

tRSTH

tPDH

MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”

VPUP

VIHMASTER

VTH

VTL

VILMAX

tREC

tMSP

After the bus master has released the line it goes into receive mode (RX). Now the 1-Wire bus is pulled to VPUP

through the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold VTH is crossed,

the DS1922L/T waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect a

presence pulse, the master must test the logical state of the 1-Wire line at tMSP.

The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the

DS1922L/T is ready for data communication. In a mixed population network tRSTH should be extended to minimum

480µs at standard speed and 48µs at Overdrive speed to accommodate other 1-Wire devices.

READ/WRITE TIME SLOTS

Data communication with the DS1922L/T takes place in time slots, which carry a single bit each. Write time slots

transport data from bus master to slave. Read time slots transfer data from slave to master. The definitions of the

write and read time slots are illustrated in Figure 13.

All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the

threshold VTL, the DS1922L/T starts its internal timing generator that determines when the data line is sampled

during a write time slot and how long data is valid during a read time slot.

DS1922L Datasheet(PDF) 39 Page - Dallas Semiconductor

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