DS1922L datasheet(41/48 Pages) DALLAS

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DS1922L/DS1922T

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The sum of tRL +

d (rise rime) on one side and the internal timing generator of the DS1922L/T on the other side

define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line.

For most reliable communication, tRL should be as short as permissible and the master should read close to but no

later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees

sufficient recovery time tREC for the DS1922L/T to get ready for the next time slot.

IMPROVED NETWORK BEHAVIOR

In a 1-Wire environment line termination is possible only during transients controlled by the bus master (1-Wire

driver). 1-Wire networks, therefore are susceptible to noise of various origins. Depending on the physical size and

topology of the network, reflections from end points, and branch points can add up or cancel each other to some

extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the

1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can

cause a slave device to lose synchronization with the master and, as a consequence, result in a search ROM

command coming to a dead end or cause a device-specific function command to abort. For better performance in

network applications, the DS1922L/T uses a new 1-Wire front end, which makes it less sensitive to noise and also

reduces the magnitude of noise injected by the slave device itself.

The 1-Wire front end of the DS1922L/T differs from traditional slave devices in four characteristics:

1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line

impedance than a digitally switched transistor, converting the high frequency ringing known from traditional

devices into a smoother low-bandwidth transition. The slew rate control is specified by the parameter tFPD,

which has different values for standard and Overdrive speed.

2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.

This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.

3) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but doesn’t go

below VTH - VHY, it will not be recognized (Figure 14, Case A). The hysteresis is effective at any 1-Wire speed.

4) There is a time window specified by the rising edge hold-off time tREH during which glitches will be ignored,

even if they extend below VTH - VHY threshold (Figure 14, Case B, tGL < tREH). Deep voltage droops or glitches

that appear late after crossing the VTH threshold and extend beyond the tREH window cannot be filtered out and

will be taken as beginning of a new time slot (Figure 14, Case C, tGL

³ tREH).

Only devices which have the parameters tFPD, VHY and tREH specified in their electrical characteristics use the

improved 1-Wire front end.

Figure 14. Noise Suppression Scheme

VPUP

VTH

VHY

tREH

tGL

tREH

tGL

Case A

Case C

Case B

DS1922L Datasheet(PDF) 41 Page - Dallas Semiconductor

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