LAN83C185 datasheet(49/61 Pages) SMSC

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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

Datasheet

SMSC LAN83C185

Rev. 0.8 (11-16-04)

DATASHEET

5.5.6.1

Functional Description

The Data recovery PLL has two modes of operation: Frequency Mode and Data Mode.

In frequency mode, the VCO locks to the external reference clock.

In Data mode, the VCO locks to the incoming data. When the PLL switches to Data mode, the VCO

is held. It is released on an incoming data edge. This provides a minimum amount of phase error when

the PLL switches from Frequency Mode to Data Mode.

5.5.7

PLL 10M - Transmit Clock

The transmit Phase Locked Loop (PLL) is used to generate a precise delay for the 10BASE-T

transmitter. It also provides a 20MHz clock for the transmit digital block.

5.5.7.1

Functional Description

This PLL is used to provide a Transmit clock to the digital and create a delay for the 10BASE-T

transmitter.

The Transmit PLL operates continuously in a frequency mode of operation where it is locked to the

input clock.

5.5.8

XMT_10

This block generates the differential outputs driven onto TXP/TXN in 10Base-T mode.

5.5.8.1

Functional Description

This block is a wave-shaped 10BASE-T transmitter, with high impedance current outputs. The low pass

filtering (wave-shaping) of the current output is done by progressive switching of small current sources.

The timing reference for the wave-shaping is the 10BASE-T transmit PLL. The transmitter is designed

to operate with a 1:1 turn-ratio transformer.

5.5.9

Central Bias

The Central Bias block generates a power-up reset signal, a PLL reset signal and the bias

currents/voltages needed by other on-chip blocks.

5.5.9.1

Functional Description

This block has three main functions: Reference bias current and voltage generator, power-up reset,

and PLL reset.

The bias generator generates accurate currents and voltages using an on-chip bandgap circuit and an

external 12.4K 1% resistor.

The power-up reset circuit generates a signal that stays high for 10 ms. This duration is controlled

through the use of counters and a 25MHz internal clock. An analog power-up circuit is used to set the

initial conditions and ensure proper startup of the circuit.

The PLL reset signal is generated after the occurrence of an active nRST. The internal reset signal is

asserted for the duration of four 25MHz clocks (160ns). It is then released. Releasing the PLL reset

early ensures that the PLL locks to the reference clock before the system reset (nRST) is released.

LAN83C185 Datasheet(PDF) 49 Page - SMSC Corporation

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