ST72561 datasheet(247/262 Pages) STMICROELECTRONICS

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ST72561

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ADC CHARACTERISTICS (Cont’d)

Figure 144. RAIN max. vs fADC with CAIN=0pF

Figure 145. Recommended CAIN/RAIN values

Figure 146. Typical Application with ADC

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

4. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

5. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and

reduced to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.

010

CPARASITIC (pF)

4 MHz

2 MHz

1 MHz

0.1

100

1000

0.01

0.1

fAIN(KHz)

Cain 10 nF

Cain 22 nF

Cain 47 nF

AINx

ST72XXX

VDD

±1

µA

0.6V

CADC

6pF

VAIN

RAIN

10-Bit A/D

Conversion

Ω(max)

CAIN

ST72561 Datasheet(PDF) 247 Page - STMicroelectronics

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