AR0130CSSC00SPBA0-DP1 datasheet(39/49 Pages) ONSEMI

39 / 49 page

AR0130CS/D Rev. 12,

1/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0130CS: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Notes:

1. Minimum and maximum values are for the spec limits: 3.1V, -30C and 2.50V, 70C. All values are

taken at the 50% transition point.

2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.

Notes:

1. Minimum and maximum values are for the spec limits: 1.95V, -30C and 1.70V, 70C. All values are

taken at the 50% transition point.

2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.

tPFL

PIXCLK to FV LOW

PIXCLK slew rate = 4

Parallel slew rate = 7

-2.5

0.5

tPLL

PIXCLK to LV LOW

PIXCLK slew rate = 4

Parallel slew rate = 7

-3.0

0.0

CLOAD

Output load capacitance

CIN

Input pin capacitance

2.5

Table 10:

I/O Timing Characteristics (1.8V VDD_IO)1

Conditions: fPIXCLK=74.25MHz (720P60fps) VDD_IO=1.8V;

slew rate setting = 4 for PIXCLK; slew rate setting = 7 for parallel ports

Symbol

Definition

Condition

Min

Typ

Max

Unit

fEXTCLK

Input clock frequency

PLL enabled

MHz

tEXTCLK

Input clock period

PLL enabled

166

Input clock rise time

-3

Input clock fall time

-3

Input clock duty cycle

tJITTER2

Input clock jitter at 27 MHz

–

600

–

tCP

EXTCLK to PIXCLK propagation

delay

Nominal voltages, PLL Disabled,

slew setting =4

fPIXCLK

PIXCLK frequency2

674.25

MHz

tRP

Pixel rise time

Slew rate setting = 4

2.50

4.30

7.10

tFP

Pixel fall time

Slew rate setting = 4

2.20

3.80

6.50

PIXCLK duty cycle

PLL enabled

tPIXJITTER

Jitter on PIXCLK

tPD

PIXCLK to data valid

PIXCLK slew rate = 4

Parallel slew rate = 7

–4.5

–

2.0

tPFH

PIXCLK to FV HIGH

PIXCLK slew rate = 4

Parallel slew rate = 7

–4.0

–

–0.5

tPLH

PIXCLK to LV HIGH

PIXCLK slew rate = 4

Parallel slew rate = 7

–4.0

–

–0.5

tPFL

PIXCLK to FV LOW

PIXCLK slew rate = 4

Parallel slew rate = 7

–4.0

–

–0.5

tPLL

PIXCLK to LV LOW

PIXCLK slew rate = 4

Parallel slew rate = 7

–4.0

–

–0.5

CLOAD

Output load capacitance

CIN

Input pin capacitance

2.5

Table 9:

I/O Timing Characteristics (2.8V VDD_IO)1 (continued)

Conditions: fPIXCLK=74.25MHz (720P60fps) VDD_IO=2.8V;

slew rate setting = 4 for PIXCLK; slew rate setting = 7 for parallel ports

Symbol

Definition

Condition

Min

Typ

Max

Unit

AR0130CSSC00SPBA0-DP1 Datasheet(PDF) 39 Page - ON Semiconductor

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